From a9989989e3e30c84d8951ad4a37ea79816847ac6 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 18 Apr 2022 13:43:40 +0530 Subject: soc/intel/alderlake: Skip FSP Notify API (post PCI enumeration) Alder Lake SoC deselects USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM Kconfig to skip FSP notify API (Post PCI Enumeration) and make use of native coreboot driver to perform SoC recommended operations prior booting to payload/OS. BUG=b:211954778 TEST=Able to build brya with these changes and coreboot log with this code change as below when ADL SoC selects required configs. [INFO ] coreboot skipped calling FSP notify phase: 00000020. Signed-off-by: Subrata Banik Change-Id: I46f6ca791fb60b417d205d0a54705f3481deebd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63693 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Lean Sheng Tan --- src/soc/intel/alderlake/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'src/soc/intel/alderlake') diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index dbcb509559..22fd9d7bb8 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -118,7 +118,6 @@ config CPU_SPECIFIC_OPTIONS select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_202005_BINDING - select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM config ALDERLAKE_CONFIGURE_DESCRIPTOR bool -- cgit v1.2.3