From 71624cd94f85b8cdad7ae59e9af6a9a509ba51c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 17 Jan 2021 01:42:15 +0100 Subject: soc/intel/*: drop broken LPC mmio code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The code for setting the LPC generic memory range uses an array of fixed address ranges not needing explicit decoding, to decide if the address needs to be written to the LGMR register. Most platforms only mistakenly add the PCH reserved mmio range, that is not decoded generally, effectively breaking the mechanism. Only APL uses the array correctly. That code, in it's current state, does not work (except for APL) and currently, there is not a single user. Thus, drop it before people start using it. Change-Id: I723415fedd1b1d95c502badf7b0510a1338b11ac Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/49588 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/alderlake/espi.c | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'src/soc/intel/alderlake') diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c index b2377274e5..b489ef6a15 100644 --- a/src/soc/intel/alderlake/espi.c +++ b/src/soc/intel/alderlake/espi.c @@ -20,21 +20,6 @@ #include #include -/* -* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve -* certain memory range as reserved range for BIOS usage. -* For this SOC, the range will be from 0FC800000h till FE7FFFFFh" -*/ -static const struct lpc_mmio_range lpc_fixed_mmio_ranges[] = { - { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, - { 0, 0 } -}; - -const struct lpc_mmio_range *soc_get_fixed_mmio_ranges() -{ - return lpc_fixed_mmio_ranges; -} - void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { const config_t *config = config_of_soc(); -- cgit v1.2.3