From 6b5b7e0654fcbc41e302539c05b258130d8bb3fe Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Mon, 6 Feb 2023 09:09:16 +0000 Subject: soc/intel/{tgl,adl}/acpi: Unify the way D3Cold is enabled Both Alder Lake and Tiger Lake have Kconfig options for S3, which disables support for D3Cold. Unify these so that they are easier to compare. Signed-off-by: Sean Rhodes Change-Id: I6eaba99e5483053a91ca20df2b7788edac5d65b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72798 Reviewed-by: Lean Sheng Tan Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/acpi/tcss.asl | 2 +- src/soc/intel/alderlake/acpi/tcss_dma.asl | 6 +++--- src/soc/intel/alderlake/acpi/tcss_pcierp.asl | 6 +++--- src/soc/intel/alderlake/acpi/tcss_xhci.asl | 4 ++-- 4 files changed, 9 insertions(+), 9 deletions(-) (limited to 'src/soc/intel/alderlake') diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index 9ef6637dce..1f626fc7d3 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -654,7 +654,7 @@ Scope (\_SB.PCI0) STAT = 0 } } -#endif +#endif // SOC_INTEL_ALDERLAKE_S3 /* * TCSS xHCI device diff --git a/src/soc/intel/alderlake/acpi/tcss_dma.asl b/src/soc/intel/alderlake/acpi/tcss_dma.asl index 989fbd5c96..1483c0b5ac 100644 --- a/src/soc/intel/alderlake/acpi/tcss_dma.asl +++ b/src/soc/intel/alderlake/acpi/tcss_dma.asl @@ -32,7 +32,7 @@ Method (_S0W, 0x0) Return (0x04) #else Return (0x03) -#endif +#endif // SOC_INTEL_ALDERLAKE_S3 } Method (_PR0) @@ -49,7 +49,7 @@ Method (_PR0) } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif +#endif // SOC_INTEL_ALDERLAKE_S3 } Method (_PR3) @@ -66,7 +66,7 @@ Method (_PR3) } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif +#endif // SOC_INTEL_ALDERLAKE_S3 } /* diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl index 7336e162a8..4f1eec5d2c 100644 --- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl @@ -251,7 +251,7 @@ Method (_S0W, 0x0, NotSerialized) Return (0x4) #else Return (0x3) -#endif +#endif // SOC_INTEL_ALDERLAKE_S3 } Method (_PR0) @@ -268,7 +268,7 @@ Method (_PR0) } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif +#endif // SOC_INTEL_ALDERLAKE_S3 } Method (_PR3) @@ -285,7 +285,7 @@ Method (_PR3) } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif +#endif // SOC_INTEL_ALDERLAKE_S3 } /* diff --git a/src/soc/intel/alderlake/acpi/tcss_xhci.asl b/src/soc/intel/alderlake/acpi/tcss_xhci.asl index 0b7aa093e1..c0dc141530 100644 --- a/src/soc/intel/alderlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/alderlake/acpi/tcss_xhci.asl @@ -34,7 +34,7 @@ Method (_S0W, 0x0, NotSerialized) Return (0x4) #else Return (0x3) -#endif +#endif // SOC_INTEL_ALDERLAKE_S3 } /* @@ -53,7 +53,7 @@ Method (_PR3) { Return (Package () { \_SB.PCI0.D3C }) } -#endif +#endif // SOC_INTEL_ALDERLAKE_S3 /* * XHCI controller _DSM method -- cgit v1.2.3