From 60d9b891f606523d82ca8d9432051b159d28342a Mon Sep 17 00:00:00 2001
From: Wonkyu Kim <wonkyu.kim@intel.com>
Date: Mon, 10 Oct 2022 23:01:38 -0700
Subject: soc/intel: Kconfig: Correct UART source clock value in comment

Correct UART source clock value in comment from 120 MHz to 100 MHz.

BUG=b:249530903

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ifc17357051ae0b3bc663da467b4fc809a46024d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68286
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/soc/intel/alderlake')

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index a73657ee2c..ca0af8a860 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -338,7 +338,7 @@ config VBT_DATA_SIZE_KB
 
 # Clock divider parameters for 115200 baud rate
 # Baudrate = (UART source clock * M) /(N *16)
-# ADL UART source clock: 120MHz
+# ADL UART source clock: 100MHz
 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
 	hex
 	default 0x25a
-- 
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