From 5ff0118a58a6ff67f0e89920403738e77e302d74 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 20 Apr 2023 11:08:17 +0530 Subject: soc/intel/(adl, cmn, mtl): Refactor cse_fw_sync() function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch refactors cse_fw_sync() function to include timestamp associated with the CSE sync operation.This effort will ensure the SoC code just makes a call into the cse_fw_sync() without bothering about adding timestamp entries. TEST=Able to build and boot google/marasov. Signed-off-by: Subrata Banik Change-Id: Ib5e8fc2b8c3b605103f7b1238df5a8405e363f83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74582 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Kapil Porwal Reviewed-by: Kangheui Won --- src/soc/intel/alderlake/romstage/romstage.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'src/soc/intel/alderlake') diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index a3273e610a..740a4a2806 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -180,11 +180,8 @@ void mainboard_romstage_entry(void) if (!CONFIG(INTEL_TXT)) disable_intel_txt(); - if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) { - timestamp_add_now(TS_CSE_FW_SYNC_START); + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) cse_fw_sync(); - timestamp_add_now(TS_CSE_FW_SYNC_END); - } /* Program to Disable UFS Controllers */ if (!is_devfn_enabled(PCH_DEVFN_UFS) && -- cgit v1.2.3