From 5e7f90bb4c24ad9c500de153df3b2304f569f6e9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 8 Jan 2022 13:16:38 +0100 Subject: soc/intel/alderlake: Factor out A0 stepping workaround Move the `configure_pmc_descriptor()` function to SoC scope instead of having two identical copies in mainboard scope. Add a Kconfig option to allow mainboards to decide whether to implement this workaround. Change-Id: Ib99073d8da91a93fae9c0cebdfd73e39456cdaa8 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/60940 Tested-by: build bot (Jenkins) Reviewed-by: Sheng Lean Tan Reviewed-by: Subrata Banik Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/Kconfig | 9 +++ src/soc/intel/alderlake/Makefile.inc | 1 + src/soc/intel/alderlake/bootblock/bootblock.c | 3 + src/soc/intel/alderlake/bootblock/pmc_descriptor.c | 89 ++++++++++++++++++++++ src/soc/intel/alderlake/include/soc/bootblock.h | 2 + 5 files changed, 104 insertions(+) create mode 100644 src/soc/intel/alderlake/bootblock/pmc_descriptor.c (limited to 'src/soc/intel/alderlake') diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 50c0c0b3e5..74c14a5ef6 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -102,6 +102,15 @@ config CPU_SPECIFIC_OPTIONS select UDK_202005_BINDING select DISPLAY_FSP_VERSION_INFO +config ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR + bool + help + Alder Lake stepping A0 needs a different value for a PMC setting in + the IFD. When this option is selected, coreboot will update the IFD + value at runtime, which allows using an IFD with the new value with + any CPU stepping. To apply this workaround, the IFD region needs to + be writable by the host. + config ALDERLAKE_CAR_ENHANCED_NEM bool default y if !INTEL_CAR_NEM diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index d2c48b74c8..095d2100f2 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -16,6 +16,7 @@ bootblock-y += bootblock/report_platform.c bootblock-y += espi.c bootblock-y += gpio.c bootblock-y += p2sb.c +bootblock-$(CONFIG_ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR) += bootblock/pmc_descriptor.c romstage-y += espi.c romstage-y += gpio.c diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c index b8086a42ab..e209ae24d7 100644 --- a/src/soc/intel/alderlake/bootblock/bootblock.c +++ b/src/soc/intel/alderlake/bootblock/bootblock.c @@ -25,6 +25,9 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { + if (CONFIG(ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR)) + configure_pmc_descriptor(); + report_platform_info(); bootblock_pch_init(); diff --git a/src/soc/intel/alderlake/bootblock/pmc_descriptor.c b/src/soc/intel/alderlake/bootblock/pmc_descriptor.c new file mode 100644 index 0000000000..4e8095750a --- /dev/null +++ b/src/soc/intel/alderlake/bootblock/pmc_descriptor.c @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SI_DESC_REGION "SI_DESC" +#define SI_DESC_REGION_SZ 4096 +#define PMC_DESC_7_BYTE3 0xc32 + +/* Flash Master 1 : HOST/BIOS */ +#define FLMSTR1 0x80 + +/* Flash signature Offset */ +#define FLASH_SIGN_OFFSET 0x10 +#define FLMSTR_WR_SHIFT_V2 20 +#define FLASH_VAL_SIGN 0xFF0A55A + +/* It checks whether host(Flash Master 1) has write access to the Descriptor Region or not */ +static int is_descriptor_writeable(uint8_t *desc) +{ + /* Check flash has valid signature */ + if (read32((void *)(desc + FLASH_SIGN_OFFSET)) != FLASH_VAL_SIGN) { + printk(BIOS_DEBUG, "Flash Descriptor is not valid\n"); + return 0; + } + + /* Check host has write access to the Descriptor Region */ + if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { + printk(BIOS_DEBUG, "Host doesn't have write access to Descriptor Region\n"); + return 0; + } + + return 1; +} + +/* It updates PMC Descriptor in the Descriptor Region */ +void configure_pmc_descriptor(void) +{ + uint8_t si_desc_buf[SI_DESC_REGION_SZ]; + struct region_device desc_rdev; + + if (cpu_get_cpuid() != CPUID_ALDERLAKE_A0) + return; + + if (fmap_locate_area_as_rdev_rw(SI_DESC_REGION, &desc_rdev) < 0) { + printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", SI_DESC_REGION); + return; + } + + if (rdev_readat(&desc_rdev, si_desc_buf, 0, SI_DESC_REGION_SZ) != SI_DESC_REGION_SZ) { + printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); + return; + } + + if (!is_descriptor_writeable(si_desc_buf)) + return; + + if (si_desc_buf[PMC_DESC_7_BYTE3] != 0x40) { + printk(BIOS_DEBUG, "Update of PMC Descriptor is not required!\n"); + return; + } + + si_desc_buf[PMC_DESC_7_BYTE3] = 0x44; + + if (rdev_eraseat(&desc_rdev, 0, SI_DESC_REGION_SZ) != SI_DESC_REGION_SZ) { + printk(BIOS_ERR, "Failed to erase Descriptor Region area\n"); + return; + } + + if (rdev_writeat(&desc_rdev, si_desc_buf, 0, SI_DESC_REGION_SZ) + != SI_DESC_REGION_SZ) { + printk(BIOS_ERR, "Failed to update Descriptor Region\n"); + return; + } + + printk(BIOS_DEBUG, "Update of PMC Descriptor successful, trigger GLOBAL RESET\n"); + + pmc_global_reset_enable(true); + do_full_reset(); + die("Failed to trigger GLOBAL RESET\n"); +} diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h index ce2e42e6b2..e989bdd865 100644 --- a/src/soc/intel/alderlake/include/soc/bootblock.h +++ b/src/soc/intel/alderlake/include/soc/bootblock.h @@ -17,4 +17,6 @@ void bootblock_pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void); +void configure_pmc_descriptor(void); + #endif -- cgit v1.2.3