From 4b2464fc90d60f01b0d890e1a0dc6dcdbd119617 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 23 Feb 2022 17:54:20 +0100 Subject: arch/x86: factor out and commonize HPET_BASE_ADDRESS definition All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000, so define this once in arch/x86 and include this wherever needed. The old AMD AGESA code in vendorcode that has its own definition is left unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common definition. Signed-off-by: Felix Held Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons Reviewed-by: Fred Reitberger --- src/soc/intel/alderlake/include/soc/iomap.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/soc/intel/alderlake') diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h index 23b7c5bc94..9ff8f54d01 100644 --- a/src/soc/intel/alderlake/include/soc/iomap.h +++ b/src/soc/intel/alderlake/include/soc/iomap.h @@ -59,8 +59,6 @@ #define REG_BASE_ADDRESS 0xfb000000 #define REG_BASE_SIZE 0x1000 -#define HPET_BASE_ADDRESS 0xfed00000 - #define PCH_PWRM_BASE_ADDRESS 0xfe000000 #define PCH_PWRM_BASE_SIZE 0x10000 -- cgit v1.2.3