From 491afc3cc778ba82154f405061922da5024357c5 Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Thu, 6 Jun 2024 12:14:39 +0530 Subject: soc/intel/alderlake: Guard PchPcieClockGating & PchPciePowerGating UPDs PchPcieClockGating & PchPciePowerGating UPDs are not available for ADL_N FSP headers. Add guard to Avoid PchPcieClockGating & PchPciePowerGating programming for ADL_N FSP. Change-Id: I2f1625038896b07c354498fe431cad97fb9b5bdb Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/82917 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Kapil Porwal --- src/soc/intel/alderlake/fsp_params.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/alderlake') diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index ff5c83c3af..d7b30c64da 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -932,7 +932,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, } s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); -#if CONFIG(FSP_TYPE_IOT) +#if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) /* * Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected. * The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1 -- cgit v1.2.3