From a1c247b55dfc182b365ac0630fc615277017631e Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 31 Dec 2020 22:50:14 -0800 Subject: soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driver This change uses the newly added meminit block driver and updates ADL SoC and mainboard code accordingly. BUG=b:172978729 Change-Id: Ibcc4ee685cdd70eac99f12a5b5d79fdbaf2b3cf6 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/49043 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Meera Ravindranath Reviewed-by: EricR Lai Reviewed-by: Subrata Banik --- src/soc/intel/alderlake/meminit.c | 365 ++++++++++++++++++++++---------------- 1 file changed, 210 insertions(+), 155 deletions(-) (limited to 'src/soc/intel/alderlake/meminit.c') diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 8473ad8a48..5b65ef063f 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -1,185 +1,240 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include -#include #include -enum dimm_enable_options { - ENABLE_BOTH_DIMMS = 0, - DISABLE_DIMM0 = 1, - DISABLE_DIMM1 = 2, - DISABLE_BOTH_DIMMS = 3 -}; +#define LPX_PHYSICAL_CH_WIDTH 16 +#define LPX_CHANNELS CHANNEL_COUNT(LPX_PHYSICAL_CH_WIDTH) -static void spd_read_from_cbfs(const struct spd_info *spd_info, - uintptr_t *spd_data_ptr, size_t *spd_data_len) -{ - struct region_device spd_rdev; - size_t spd_index = spd_info->spd_spec.spd_index; +#define DDR4_PHYSICAL_CH_WIDTH 64 +#define DDR4_CHANNELS CHANNEL_COUNT(DDR4_PHYSICAL_CH_WIDTH) - printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) - die("spd.bin not found or incorrect index\n"); +#define DDR5_PHYSICAL_CH_WIDTH 32 +#define DDR5_CHANNELS CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH) - *spd_data_len = region_device_sz(&spd_rdev); +static void meminit_lp4x(FSP_M_CONFIG *mem_cfg) +{ + mem_cfg->DqPinsInterleaved = 0; +} - /* Memory leak is ok since we have memory mapped boot media */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); +static void meminit_lp5x(FSP_M_CONFIG *mem_cfg, const struct mem_lp5x_config *lp5x_config) +{ + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->Lp5CccConfig = lp5x_config->ccc_config; +} - *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); +static void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct mem_ddr_config *ddr_config) +{ + mem_cfg->DqPinsInterleaved = ddr_config->dq_pins_interleaved; + memcpy(&mem_cfg->RcompResistor, ddr_config->rcomp_resistor, + sizeof(mem_cfg->RcompResistor)); + memcpy(&mem_cfg->RcompTarget, ddr_config->rcomp_targets, sizeof(mem_cfg->RcompTarget)); } -static void get_spd_data(const struct spd_info *spd_info, - uintptr_t *spd_data_ptr, size_t *spd_data_len) +static const struct soc_mem_cfg soc_mem_cfg[] = { + [MEM_TYPE_DDR4] = { + .num_phys_channels = DDR4_CHANNELS, + .phys_to_mrc_map = { + [0] = 0, + [1] = 4, + }, + .md_phy_masks = { + /* + * Only physical channel 0 is populated in case of half-populated + * configuration. + */ + .half_channel = BIT(0), + /* In mixed topologies, channel 1 is always memory-down. */ + .mixed_topo = BIT(1), + }, + }, + [MEM_TYPE_DDR5] = { + .num_phys_channels = DDR5_CHANNELS, + .phys_to_mrc_map = { + [0] = 0, + [1] = 1, + [2] = 4, + [3] = 5, + }, + .md_phy_masks = { + /* + * Physical channels 0 and 1 are populated in case of + * half-populated configurations. + */ + .half_channel = BIT(0) | BIT(1), + /* In mixed topologies, channels 2 and 3 are always memory-down. */ + .mixed_topo = BIT(2) | BIT(3), + }, + }, + [MEM_TYPE_LP4X] = { + .num_phys_channels = LPX_CHANNELS, + .phys_to_mrc_map = { + [0] = 0, + [1] = 1, + [2] = 2, + [3] = 3, + [4] = 4, + [5] = 5, + [6] = 6, + [7] = 7, + }, + .md_phy_masks = { + /* + * Physical channels 0, 1, 2 and 3 are populated in case of + * half-populated configurations. + */ + .half_channel = BIT(0) | BIT(1) | BIT(2) | BIT(3), + /* LP4x does not support mixed topologies. */ + }, + }, + [MEM_TYPE_LP5X] = { + .num_phys_channels = LPX_CHANNELS, + .phys_to_mrc_map = { + [0] = 0, + [1] = 1, + [2] = 2, + [3] = 3, + [4] = 4, + [5] = 5, + [6] = 6, + [7] = 7, + }, + .md_phy_masks = { + /* + * Physical channels 0, 1, 2 and 3 are populated in case of + * half-populated configurations. + */ + .half_channel = BIT(0) | BIT(1) | BIT(2) | BIT(3), + /* LP5x does not support mixed topologies. */ + }, + }, +}; + +static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data) { - if (spd_info->read_type == READ_SPD_MEMPTR) { - *spd_data_ptr = spd_info->spd_spec.spd_data_ptr_info.spd_data_ptr; - *spd_data_len = spd_info->spd_spec.spd_data_ptr_info.spd_data_len; - return; + uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = { + [0] = { &mem_cfg->MemorySpdPtr00, &mem_cfg->MemorySpdPtr01, }, + [1] = { &mem_cfg->MemorySpdPtr02, &mem_cfg->MemorySpdPtr03, }, + [2] = { &mem_cfg->MemorySpdPtr04, &mem_cfg->MemorySpdPtr05, }, + [3] = { &mem_cfg->MemorySpdPtr06, &mem_cfg->MemorySpdPtr07, }, + [4] = { &mem_cfg->MemorySpdPtr08, &mem_cfg->MemorySpdPtr09, }, + [5] = { &mem_cfg->MemorySpdPtr10, &mem_cfg->MemorySpdPtr11, }, + [6] = { &mem_cfg->MemorySpdPtr12, &mem_cfg->MemorySpdPtr13, }, + [7] = { &mem_cfg->MemorySpdPtr14, &mem_cfg->MemorySpdPtr15, }, + }; + uint8_t *disable_dimm_upds[MRC_CHANNELS] = { + &mem_cfg->DisableDimmMc0Ch0, + &mem_cfg->DisableDimmMc0Ch1, + &mem_cfg->DisableDimmMc0Ch2, + &mem_cfg->DisableDimmMc0Ch3, + &mem_cfg->DisableDimmMc1Ch0, + &mem_cfg->DisableDimmMc1Ch1, + &mem_cfg->DisableDimmMc1Ch2, + &mem_cfg->DisableDimmMc1Ch3, + }; + size_t ch, dimm; + + mem_cfg->MemorySpdDataLen = data->spd_len; + + for (ch = 0; ch < MRC_CHANNELS; ch++) { + uint8_t *disable_dimm_ptr = disable_dimm_upds[ch]; + *disable_dimm_ptr = 0; + + for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { + uint32_t *spd_ptr = spd_upds[ch][dimm]; + + *spd_ptr = data->spd[ch][dimm]; + if (!*spd_ptr) + *disable_dimm_ptr |= BIT(dimm); + } } +} - if (spd_info->read_type == READ_SPD_CBFS) { - spd_read_from_cbfs(spd_info, spd_data_ptr, spd_data_len); - return; +static void mem_init_dq_dqs_upds(void *upds[MRC_CHANNELS], const void *map, size_t upd_size, + const struct mem_channel_data *data, bool auto_detect) +{ + size_t i; + + for (i = 0; i < MRC_CHANNELS; i++, map += upd_size) { + if (auto_detect || + !channel_is_populated(i, MRC_CHANNELS, data->ch_population_flags)) + memset(upds[i], 0, upd_size); + else + memcpy(upds[i], map, upd_size); } } -static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg, - const struct mb_cfg *board_cfg, - bool half_populated) +static void mem_init_dq_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data, + const struct mb_cfg *mb_cfg, bool auto_detect) { - memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor, - sizeof(mem_cfg->RcompResistor)); - - memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets, - sizeof(mem_cfg->RcompTarget)); - - memcpy(&mem_cfg->DqMapCpu2DramCh0, &board_cfg->dq_map[DDR_CH0], - sizeof(board_cfg->dq_map[DDR_CH0])); - memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0], - sizeof(board_cfg->dqs_map[DDR_CH0])); - - memcpy(&mem_cfg->DqMapCpu2DramCh1, &board_cfg->dq_map[DDR_CH1], - sizeof(board_cfg->dq_map[DDR_CH1])); - memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1], - sizeof(board_cfg->dqs_map[DDR_CH1])); - - memcpy(&mem_cfg->DqMapCpu2DramCh2, &board_cfg->dq_map[DDR_CH2], - sizeof(board_cfg->dq_map[DDR_CH2])); - memcpy(&mem_cfg->DqsMapCpu2DramCh2, &board_cfg->dqs_map[DDR_CH2], - sizeof(board_cfg->dqs_map[DDR_CH2])); - - memcpy(&mem_cfg->DqMapCpu2DramCh3, &board_cfg->dq_map[DDR_CH3], - sizeof(board_cfg->dq_map[DDR_CH3])); - memcpy(&mem_cfg->DqsMapCpu2DramCh3, &board_cfg->dqs_map[DDR_CH3], - sizeof(board_cfg->dqs_map[DDR_CH3])); - - if (half_populated) - return; - - memcpy(&mem_cfg->DqMapCpu2DramCh4, &board_cfg->dq_map[DDR_CH4], - sizeof(board_cfg->dq_map[DDR_CH4])); - memcpy(&mem_cfg->DqsMapCpu2DramCh4, &board_cfg->dqs_map[DDR_CH4], - sizeof(board_cfg->dqs_map[DDR_CH4])); - - memcpy(&mem_cfg->DqMapCpu2DramCh5, &board_cfg->dq_map[DDR_CH5], - sizeof(board_cfg->dq_map[DDR_CH5])); - memcpy(&mem_cfg->DqsMapCpu2DramCh5, &board_cfg->dqs_map[DDR_CH5], - sizeof(board_cfg->dqs_map[DDR_CH5])); - - memcpy(&mem_cfg->DqMapCpu2DramCh6, &board_cfg->dq_map[DDR_CH6], - sizeof(board_cfg->dq_map[DDR_CH6])); - memcpy(&mem_cfg->DqsMapCpu2DramCh6, &board_cfg->dqs_map[DDR_CH6], - sizeof(board_cfg->dqs_map[DDR_CH6])); - - memcpy(&mem_cfg->DqMapCpu2DramCh7, &board_cfg->dq_map[DDR_CH7], - sizeof(board_cfg->dq_map[DDR_CH7])); - memcpy(&mem_cfg->DqsMapCpu2DramCh7, &board_cfg->dqs_map[DDR_CH7], - sizeof(board_cfg->dqs_map[DDR_CH7])); + void *dq_upds[MRC_CHANNELS] = { + &mem_cfg->DqMapCpu2DramCh0, + &mem_cfg->DqMapCpu2DramCh1, + &mem_cfg->DqMapCpu2DramCh2, + &mem_cfg->DqMapCpu2DramCh3, + &mem_cfg->DqMapCpu2DramCh4, + &mem_cfg->DqMapCpu2DramCh5, + &mem_cfg->DqMapCpu2DramCh6, + &mem_cfg->DqMapCpu2DramCh7, + }; + + const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramCh0); + + _Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH, "Incorrect DQ UPD size!"); + + mem_init_dq_dqs_upds(dq_upds, mb_cfg->dq_map, upd_size, data, auto_detect); } -static void meminit_channels(FSP_M_CONFIG *mem_cfg, - const struct mb_cfg *board_cfg, - uintptr_t spd_data_ptr, - bool half_populated) +static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data, + const struct mb_cfg *mb_cfg, bool auto_detect) { - uint8_t dimm_cfg = DISABLE_DIMM1; /* Use only DIMM0 */ - - /* Channel 0 */ - mem_cfg->DisableDimmMc0Ch0 = dimm_cfg; - mem_cfg->MemorySpdPtr00 = spd_data_ptr; - mem_cfg->MemorySpdPtr01 = 0; - - /* Channel 1 */ - mem_cfg->DisableDimmMc0Ch1 = dimm_cfg; - mem_cfg->MemorySpdPtr02 = spd_data_ptr; - mem_cfg->MemorySpdPtr03 = 0; - - /* Channel 2 */ - mem_cfg->DisableDimmMc0Ch2 = dimm_cfg; - mem_cfg->MemorySpdPtr04 = spd_data_ptr; - mem_cfg->MemorySpdPtr05 = 0; - - /* Channel 3 */ - mem_cfg->DisableDimmMc0Ch3 = dimm_cfg; - mem_cfg->MemorySpdPtr06 = spd_data_ptr; - mem_cfg->MemorySpdPtr07 = 0; - - if (half_populated) { - printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__); - dimm_cfg = DISABLE_BOTH_DIMMS; - spd_data_ptr = 0; - } - - /* Channel 4 */ - mem_cfg->DisableDimmMc1Ch0 = dimm_cfg; - mem_cfg->MemorySpdPtr08 = spd_data_ptr; - mem_cfg->MemorySpdPtr09 = 0; - - /* Channel 5 */ - mem_cfg->DisableDimmMc1Ch1 = dimm_cfg; - mem_cfg->MemorySpdPtr10 = spd_data_ptr; - mem_cfg->MemorySpdPtr11 = 0; - - /* Channel 6 */ - mem_cfg->DisableDimmMc1Ch2 = dimm_cfg; - mem_cfg->MemorySpdPtr12 = spd_data_ptr; - mem_cfg->MemorySpdPtr13 = 0; - - /* Channel 7 */ - mem_cfg->DisableDimmMc1Ch3 = dimm_cfg; - mem_cfg->MemorySpdPtr14 = spd_data_ptr; - mem_cfg->MemorySpdPtr15 = 0; - - meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); + void *dqs_upds[MRC_CHANNELS] = { + &mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1, + &mem_cfg->DqsMapCpu2DramCh2, + &mem_cfg->DqsMapCpu2DramCh3, + &mem_cfg->DqsMapCpu2DramCh4, + &mem_cfg->DqsMapCpu2DramCh5, + &mem_cfg->DqsMapCpu2DramCh6, + &mem_cfg->DqsMapCpu2DramCh7, + }; + + const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramCh0); + + _Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH / 8, "Incorrect DQS UPD size!"); + + mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect); } -/* Initialize onboard memory configurations for lpddr4x */ -void memcfg_init(FSP_M_CONFIG *mem_cfg, - const struct mb_cfg *board_cfg, - const struct spd_info *spd_info, - bool half_populated) +void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, + const struct mem_spd *spd_info, bool half_populated) { - if (spd_info->read_type == READ_SMBUS) { - for (int i = 0; i < NUM_DIMM_SLOT; i++) - mem_cfg->SpdAddressTable[i] = spd_info->spd_spec.spd_smbus_address[i]; - meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); - } else { - size_t spd_data_len = 0; - uintptr_t spd_data_ptr = 0; - - memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable)); - get_spd_data(spd_info, &spd_data_ptr, &spd_data_len); - - mem_cfg->MemorySpdDataLen = spd_data_len; - meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated); + struct mem_channel_data data; + bool dq_dqs_auto_detect = false; + + mem_cfg->ECT = mb_cfg->ect; + mem_cfg->UserBd = mb_cfg->UserBd; + + switch (mb_cfg->type) { + case MEM_TYPE_DDR4: + case MEM_TYPE_DDR5: + meminit_ddr(mem_cfg, &mb_cfg->ddr_config); + dq_dqs_auto_detect = true; + break; + case MEM_TYPE_LP4X: + meminit_lp4x(mem_cfg); + break; + case MEM_TYPE_LP5X: + meminit_lp5x(mem_cfg, &mb_cfg->lp5x_config); + break; + default: + die("Unsupported memory type(%d)\n", mb_cfg->type); } - mem_cfg->Lp5CccConfig = board_cfg->lp5_ccc_config; - mem_cfg->ECT = board_cfg->ect; - mem_cfg->UserBd = board_cfg->UserBd; - mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved; + mem_populate_channel_data(&soc_mem_cfg[mb_cfg->type], spd_info, half_populated, &data); + mem_init_spd_upds(mem_cfg, &data); + mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); + mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); 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