From f8d4b50a67858f020bc83a4176cca1e3d40bf703 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 23 May 2022 11:53:17 +0530 Subject: soc/intel/alderlake: Drop unused `PCH_DEV_SLOT_LPC` macro This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the Alder Lake SoC PCI device list. BUG=none TEST=Able to build and boot taeko, google board. Signed-off-by: Subrata Banik Change-Id: Ib2ae40fcc4499de34534f27f03b4c359c37409e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64586 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/soc/intel/alderlake/include/soc/pci_devs.h | 1 - 1 file changed, 1 deletion(-) (limited to 'src/soc/intel/alderlake/include') diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index b7196df0c3..ea1053b84f 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -211,7 +211,6 @@ #define PCH_DEV_GSPI1 _PCH_DEV(SIO5, 3) #define PCH_DEV_SLOT_ESPI 0x1f -#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI #define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0) #define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1) #define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2) -- cgit v1.2.3