From c6b65c1a811e25dc909659ff4890eb76e16dba8a Mon Sep 17 00:00:00 2001 From: Anil Kumar Date: Tue, 1 Feb 2022 12:59:03 -0800 Subject: soc/intel/alderlake: Enable USB2 port reset message on Type-C ports This change is added to address the issue of USB3 ports downgrading to high speed during low power modes and not returning back to super speed. The patch enables port reset event on USB2 ports. This event is is passed to USB3 upstream ports to upgrade back to super speed (USB3) after a downgrade during low power state BUG=b:193287279 TEST=Built coreboot on Gimble and tested type A pen drive detects as super speed device Change-Id: Iabc6f308992bf3868da66f152c6d7b0164e64bea Signed-off-by: Anil Kumar Reviewed-on: https://review.coreboot.org/c/coreboot/+/61536 Tested-by: build bot (Jenkins) Reviewed-by: Sridhar Siricilla Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/include/soc/usb.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/alderlake/include') diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h index e339c7261e..70a367ec59 100644 --- a/src/soc/intel/alderlake/include/soc/usb.h +++ b/src/soc/intel/alderlake/include/soc/usb.h @@ -31,6 +31,7 @@ struct usb2_port_config { uint8_t tx_emp_enable; uint8_t pre_emp_bias; uint8_t pre_emp_bit; + uint8_t type_c; }; /* USB Overcurrent pins definition */ @@ -112,6 +113,7 @@ enum { .tx_emp_enable = USB2_PRE_EMP_ON, \ .pre_emp_bias = USB2_BIAS_56P3MV, \ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ + .type_c = 1, \ } struct usb3_port_config { -- cgit v1.2.3