From 9d4fda857929d286fa5a367d0ca6611e2949aa12 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Fri, 9 Jul 2021 10:18:44 -0600 Subject: soc/intel/alderlake: Add missing devices to pci_devs.h There were some devices missing from pci_devs.h: 1) GNA 2) I2C6 and I2C7 3) UART3, UART4, UART5, UART6 4) UFS 5) GSPI4, GSPI5, GSPI6 BUG=b:176858827 Signed-off-by: Tim Wawrzynczak Change-Id: I2b9f8cceb4bd0c77fc43ef2e48190dd736a84ad8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56172 Reviewed-by: Furquan Shaikh Reviewed-by: EricR Lai Reviewed-by: Maulik V Vaghela Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/include/soc/pci_devs.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'src/soc/intel/alderlake/include') diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index 1e8ecc7266..1729160634 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -56,6 +56,10 @@ #define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) +#define SA_DEV_SLOT_GNA 0x08 +#define SA_DEVFN_GNA PCI_DEVFN(SA_DEV_SLOT_GNA, 0) +#define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0) + #define SA_DEV_SLOT_TMT 0x0A #define SA_DEVFN_TMT _SA_DEVFN(TMT) #define SA_DEV_TMT _SA_DEV(TMT) @@ -79,20 +83,42 @@ /* PCH Devices */ #define MIN_PCH_SLOT PCH_DEV_SLOT_SIO0 #define PCH_DEV_SLOT_SIO0 0x10 +#define PCH_DEVFN_I2C6 _PCH_DEVFN(SIO0, 0) +#define PCH_DEVFN_I2C7 _PCH_DEVFN(SIO0, 1) #define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6) #define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7) +#define PCH_DEV_I2C6 _PCH_DEV(SIO0, 0) +#define PCH_DEV_I2C7 _PCH_DEV(SIO0, 1) #define PCH_DEV_THC0 _PCH_DEV(SIO0, 6) #define PCH_DEV_THC1 _PCH_DEV(SIO0, 7) +#define PCH_DEV_SLOT_SIO6 0x11 +#define PCH_DEVFN_UART3 _PCH_DEVFN(SIO6, 0) +#define PCH_DEVFN_UART4 _PCH_DEVFN(SIO6, 1) +#define PCH_DEVFN_UART5 _PCH_DEVFN(SIO6, 2) +#define PCH_DEVFN_UART6 _PCH_DEVFN(SIO6, 3) +#define PCH_DEV_UART3 _PCH_DEV(SIO6, 0) +#define PCH_DEV_UART4 _PCH_DEV(SIO6, 1) +#define PCH_DEV_UART5 _PCH_DEV(SIO6, 2) +#define PCH_DEV_UART6 _PCH_DEV(SIO6, 3) + #define PCH_DEV_SLOT_ISH 0x12 #define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) #define PCH_DEVFN_GSPI2 _PCH_DEVFN(ISH, 6) +#define PCH_DEVFN_UFS _PCH_DEVFN(ISH, 7) #define PCH_DEV_ISH _PCH_DEV(ISH, 0) #define PCH_DEV_GSPI2 _PCH_DEV(ISH, 6) +#define PCH_DEV_UFS _PCH_DEV(ISH, 7) #define PCH_DEV_SLOT_SIO2 0x13 #define PCH_DEVFN_GSPI3 _PCH_DEVFN(SIO2, 0) +#define PCH_DEVFN_GSPI4 _PCH_DEVFN(SIO2, 1) +#define PCH_DEVFN_GSPI5 _PCH_DEVFN(SIO2, 2) +#define PCH_DEVFN_GSPI6 _PCH_DEVFN(SIO2, 3) #define PCH_DEV_GSPI3 _PCH_DEV(SIO2, 0) +#define PCH_DEV_GSPI4 _PCH_DEV(SIO2, 1) +#define PCH_DEV_GSPI5 _PCH_DEV(SIO2, 2) +#define PCH_DEV_GSPI6 _PCH_DEV(SIO2, 3) #define PCH_DEV_SLOT_XHCI 0x14 #define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) -- cgit v1.2.3