From 8e7facf3437d633af747f6163cd66525ea14860e Mon Sep 17 00:00:00 2001 From: Deepti Deshatty Date: Wed, 12 May 2021 17:45:37 +0530 Subject: soc/intel/alderlake: mb/intel/sm: Add tcss code Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during silicon init. Type-c aux lines DC bias changes are propagated from tigerlake platform. TEST=Verified superspeed pendrive detection on coldboot. Signed-off-by: Deepti Deshatty Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/include/soc/tcss.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 src/soc/intel/alderlake/include/soc/tcss.h (limited to 'src/soc/intel/alderlake/include') diff --git a/src/soc/intel/alderlake/include/soc/tcss.h b/src/soc/intel/alderlake/include/soc/tcss.h new file mode 100644 index 0000000000..713528bdbb --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/tcss.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_TCSS_H_ +#define _SOC_TCSS_H_ + +/* IOM aux bias control registers in REGBAR MMIO space */ +#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 0x1070 +#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 + (x) * 4) +#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 0x1088 +#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4) + +#endif /* _SOC_TCSS_H_ */ -- cgit v1.2.3