From 0b11ff8aa830ca6902c246e14d44c57bc59dd0a3 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 5 Oct 2020 19:32:06 +0530 Subject: soc/intel/alderlake/ramstage: Fix compilation issue Refer to commit 0359d9d (soc/intel: Make use of PMC low power program from common block) commit 1366e44 (soc/intel: Move pch_enable_ioapic() to common code) commit 78463a7 (soc/intel: Move soc_pch_pirq_init() to common code) commit 8971ccd (soc/intel: Move pch_misc_init() to common code) for details Change-Id: Ic83d332cf2bfe8eded1667dd1503e718d854f10b Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46053 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/alderlake/include/soc/pmc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/alderlake/include') diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h index e4e3dfb690..8887d9bd1c 100644 --- a/src/soc/intel/alderlake/include/soc/pmc.h +++ b/src/soc/intel/alderlake/include/soc/pmc.h @@ -125,6 +125,7 @@ enum pch_pmc_xtal { enum pch_pmc_xtal pmc_get_xtal_freq(void); #define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x1920 #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) -- cgit v1.2.3