From 2871e0e78c309041a0f3d6e0d7dca99bcaf9f12a Mon Sep 17 00:00:00 2001
From: Subrata Banik <subrata.banik@intel.com>
Date: Sun, 27 Sep 2020 11:30:58 +0530
Subject: soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage

List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Add CPU, PCH and SA EDS document number and chapter number
4. Fill required FSP-S UPD to call FSP-S API

Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/alderlake/i2c.c | 49 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 src/soc/intel/alderlake/i2c.c

(limited to 'src/soc/intel/alderlake/i2c.c')

diff --git a/src/soc/intel/alderlake/i2c.c b/src/soc/intel/alderlake/i2c.c
new file mode 100644
index 0000000000..ef34e2ef1c
--- /dev/null
+++ b/src/soc/intel/alderlake/i2c.c
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on Intel Alder Lake Processor PCH Datasheet
+ * Document number: 621483
+ * Chapter number: 13
+ */
+
+#include <device/device.h>
+#include <drivers/i2c/designware/dw_i2c.h>
+#include <soc/pci_devs.h>
+
+int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
+{
+	switch (devfn) {
+	case PCH_DEVFN_I2C0:
+		return 0;
+	case PCH_DEVFN_I2C1:
+		return 1;
+	case PCH_DEVFN_I2C2:
+		return 2;
+	case PCH_DEVFN_I2C3:
+		return 3;
+	case PCH_DEVFN_I2C4:
+		return 4;
+	case PCH_DEVFN_I2C5:
+		return 5;
+	}
+	return -1;
+}
+
+int dw_i2c_soc_bus_to_devfn(unsigned int bus)
+{
+	switch (bus) {
+	case 0:
+		return PCH_DEVFN_I2C0;
+	case 1:
+		return PCH_DEVFN_I2C1;
+	case 2:
+		return PCH_DEVFN_I2C2;
+	case 3:
+		return PCH_DEVFN_I2C3;
+	case 4:
+		return PCH_DEVFN_I2C4;
+	case 5:
+		return PCH_DEVFN_I2C5;
+	}
+	return -1;
+}
-- 
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