From 091dfa1ca027d93fc6a78ded758b6ccd49c0f72a Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 24 Aug 2021 09:32:09 -0600 Subject: soc/intel/alderlake: Lock PAM registers in finalize Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. TEST=boot to OS, read PCI 0:0.0 config register 0x80, value is 0x31 Signed-off-by: Tim Wawrzynczak Change-Id: I0c3e16edeab6f85a79eb10e1477d95952b554a18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57146 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Furquan Shaikh --- src/soc/intel/alderlake/fsp_params.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/alderlake/fsp_params.c') diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 3accdbb408..7e1afde38b 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -406,6 +406,7 @@ static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, s_cfg->PchLockDownBiosInterface = lockdown_by_fsp; s_cfg->PchUnlockGpioPads = !lockdown_by_fsp; s_cfg->RtcMemoryLock = lockdown_by_fsp; + s_cfg->SkipPamLock = !lockdown_by_fsp; /* coreboot will send EOP before loading payload */ s_cfg->EndOfPostMessage = EOP_DISABLE; -- cgit v1.2.3