From 8913b783b9d3ffea2eda7cfd1c9e7319ae889246 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 11 Dec 2020 22:13:44 +0100 Subject: soc/intel: hook up new gpio device in the soc chips MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change adds the required gpio operations struct to soc/common gpio code and hooks them up in all socs currently using the gpio block code, except DNV-NS, which is handled in a separate change. Also, add the gpio device to existing chipset devicetrees. Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with CB:48711 and OCP DeltaLake with CB:48672. Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Tested-by: Johnny Lin Tested-by: Michael Niewöhner Tested-by: Patrick Rudolph Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/48583 Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/chipset.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/alderlake/chipset.cb') diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index de97a5780b..173d3e037f 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -1,5 +1,6 @@ chip soc/intel/alderlake device domain 0 on + device gpio 0 alias pch_gpio on end device pci 00.0 alias system_agent on end device pci 01.0 alias pcie5 off end device pci 02.0 alias igpu off end -- cgit v1.2.3