From 4a48dbe60bb39b2114f1a4c9bfc02a8d1a8e258f Mon Sep 17 00:00:00 2001 From: Ryan Lin Date: Tue, 28 Sep 2021 15:59:34 +0800 Subject: src/soc/intel/alderlake: Add PsysPmax setting This patch feeds PsysPmax setting to FSP through UPD and adds a PsysPmax member in chip information so that we can set PsysPmax through devicetree. The PsysPmax needs to be set correctly mapping to maximum system power. Otherwise, system performance would be limited due to the default PsysPmax setting in FSP is only 21W. BUG=b:193864533, b:195615830 TEST=Set PsysPmax to an example value eg 145 in devicetree && put debug code in FSP to print the PsysPmax value before sending to Pcode, ensure the setting is correctly programmed. Change-Id: Ia07aa815f90739240f110cab984068237c02d896 Signed-off-by: Ryan Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/58008 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/chip.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/alderlake/chip.h') diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 3192478f77..270400b341 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -492,6 +492,9 @@ struct soc_intel_alderlake_config { POWER_CYCLE_DURATION_3S, POWER_CYCLE_DURATION_4S, } pch_reset_power_cycle_duration; + + /* Platform Power Pmax */ + uint16_t PsysPmax; }; typedef struct soc_intel_alderlake_config config_t; -- cgit v1.2.3