From b3ced6a67b6f950d06bebf413d98218969b75b57 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 4 Aug 2020 13:34:03 +0530 Subject: soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock List of changes: 1. Add required SoC programming till bootblock 2. Include only required headers into include/soc 3. Add CPU/PCH/SA EDS document number and chapter number 4. Include ADL-P related DID, BDF Signed-off-by: Subrata Banik Change-Id: I204e692fabb84fce297bebee465f4ca624c6fe56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44857 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/bootblock/bootblock.c | 32 ++++ src/soc/intel/alderlake/bootblock/cpu.c | 20 +++ src/soc/intel/alderlake/bootblock/pch.c | 153 ++++++++++++++++ .../intel/alderlake/bootblock/report_platform.c | 200 +++++++++++++++++++++ 4 files changed, 405 insertions(+) create mode 100644 src/soc/intel/alderlake/bootblock/bootblock.c create mode 100644 src/soc/intel/alderlake/bootblock/cpu.c create mode 100644 src/soc/intel/alderlake/bootblock/pch.c create mode 100644 src/soc/intel/alderlake/bootblock/report_platform.c (limited to 'src/soc/intel/alderlake/bootblock') diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c new file mode 100644 index 0000000000..e7d97c50bf --- /dev/null +++ b/src/soc/intel/alderlake/bootblock/bootblock.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + /* Call lib/bootblock.c main */ + bootblock_main_with_basetime(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + bootblock_systemagent_early_init(); + bootblock_pch_early_init(); + bootblock_cpu_init(); + pch_early_iorange_init(); + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + uart_bootblock_init(); +} + +void bootblock_soc_init(void) +{ + report_platform_info(); + pch_init(); + + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); +} diff --git a/src/soc/intel/alderlake/bootblock/cpu.c b/src/soc/intel/alderlake/bootblock/cpu.c new file mode 100644 index 0000000000..4225358de5 --- /dev/null +++ b/src/soc/intel/alderlake/bootblock/cpu.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 7 + */ + +#include +#include + +void bootblock_cpu_init(void) +{ + /* + * Alderlake platform doesn't support booting from any other media + * than SPI flash and on IA platform SPI is memory mapped hence + * enabling temporary caching of memory-mapped spi boot media. + */ + fast_spi_cache_bios_region(); +} diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c new file mode 100644 index 0000000000..8452d83290 --- /dev/null +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 2, 3, 4, 27, 28 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1100 +#define PCR_PSFX_TO_SHDW_BAR0 0 +#define PCR_PSFX_TO_SHDW_BAR1 0x4 +#define PCR_PSFX_TO_SHDW_BAR2 0x8 +#define PCR_PSFX_TO_SHDW_BAR3 0xC +#define PCR_PSFX_TO_SHDW_BAR4 0x10 +#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 +#define PCR_PSFX_T0_SHDW_PCIEN 0x1C + +#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) + +#define PCR_DMI_ACPIBA 0x27B4 +#define PCR_DMI_ACPIBDID 0x27B8 +#define PCR_DMI_PMBASEA 0x27AC +#define PCR_DMI_PMBASEC 0x27B0 + +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 + +static void soc_config_pwrmbase(void) +{ + /* + * Assign Resources to PWRMBASE + * Clear BIT 1-2 Command Register + */ + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); + + /* Program PWRM Base */ + pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); + + /* Enable Bus Master and MMIO Space */ + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); + + /* Enable PWRM in PMC */ + setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); +} + +void bootblock_pch_early_init(void) +{ + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + p2sb_enable_bar(); + p2sb_configure_hpet(); + + /* + * Enabling PWRM Base for accessing + * Global Reset Cause Register. + */ + soc_config_pwrmbase(); +} + +static void soc_config_acpibase(void) +{ + uint32_t pmc_reg_value; + uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE; + + pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); + + if (pmc_reg_value != 0xffffffff) { + /* Disable Io Space before changing the address */ + pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, + ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); + /* Program ABASE in PSF3 PMC space BAR4*/ + pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4, + ACPI_BASE_ADDRESS); + /* Enable IO Space */ + pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, + ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); + } +} + +static int pch_check_decode_enable(void) +{ + const uint32_t dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); + + /* + * This cycle decoding is only allowed to set when + * DMICTL.SRLOCK is 0. + */ + if (dmi_control & PCR_DMI_DMICTL_SRLOCK) + return -1; + return 0; +} + +void pch_early_iorange_init(void) +{ + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | + LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; + + /* IO Decode Range */ + if (CONFIG(DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); + + /* IO Decode Enable */ + if (pch_check_decode_enable() == 0) { + io_enables = lpc_enable_fixed_io_ranges(io_enables); + /* + * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in ESPI PCI offset 82h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + /* + * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same + * value programmed in LPC PCI offset 80h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); + } + + /* Program generic IO Decode Range */ + pch_enable_lpc(); +} + +void pch_init(void) +{ + /* + * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, + * GPE0_STS, GPE0_EN registers. + */ + soc_config_acpibase(); + + /* Set up GPE configuration */ + pmc_gpe_init(); + + enable_rtc_upper_bank(); +} diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c new file mode 100644 index 0000000000..38e909c73d --- /dev/null +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -0,0 +1,200 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Platform Stepping and IDs + * Document number: 619362, 619501 + * Chapter number: 2, 14 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct { + u32 cpuid; + const char *name; +} cpu_table[] = { + { CPUID_ALDERLAKE_P_A0, "Alderlake-P A0" }, +}; + +static struct { + u16 mchid; + const char *name; +} mch_table[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, "Alderlake-P" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_2, "Alderlake-P" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, "Alderlake-P" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, "Alderlake-P" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, "Alderlake-P" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, "Alderlake-P" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, "Alderlake-P" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_8, "Alderlake-P" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_9, "Alderlake-P" }, +}; + +static struct { + u16 espiid; + const char *name; +} pch_table[] = { + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_0, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_1, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_2, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_3, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_4, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_5, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_6, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_7, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_8, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_9, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_10, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_11, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_12, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_13, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_14, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_15, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_16, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_17, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_18, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_19, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_20, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_21, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_22, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_23, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_24, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_25, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_26, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_27, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_28, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, "Alderlake-P SKU" }, +}; + +static struct { + u16 igdid; + const char *name; +} igd_table[] = { + { PCI_DEVICE_ID_INTEL_ADL_GT0, "Alderlake GT0" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_1, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_2, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_3, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_4, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_5, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_6, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_7, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_8, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_9, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_P_GT2, "Alderlake P GT2" }, +}; + +static inline uint8_t get_dev_revision(pci_devfn_t dev) +{ + return pci_read_config8(dev, PCI_REVISION_ID); +} + +static inline uint16_t get_dev_id(pci_devfn_t dev) +{ + return pci_read_config16(dev, PCI_DEVICE_ID); +} + +static void report_cpu_info(void) +{ + u32 i, cpu_id, cpu_feature_flag; + char cpu_name[49]; + int vt, txt, aes; + static const char *const mode[] = {"NOT ", ""}; + const char *cpu_type = "Unknown"; + + fill_processor_name(cpu_name); + cpu_id = cpu_get_cpuid(); + + /* Look for string to match the name */ + for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { + if (cpu_table[i].cpuid == cpu_id) { + cpu_type = cpu_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); + printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", + cpu_id, cpu_type, get_current_microcode_rev()); + + cpu_feature_flag = cpu_get_feature_flags_ecx(); + aes = !!(cpu_feature_flag & CPUID_AES); + txt = !!(cpu_feature_flag & CPUID_SMX); + vt = !!(cpu_feature_flag & CPUID_VMX); + printk(BIOS_DEBUG, + "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); +} + +static void report_mch_info(void) +{ + int i; + uint16_t mchid = get_dev_id(SA_DEV_ROOT); + const char *mch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(mch_table); i++) { + if (mch_table[i].mchid == mchid) { + mch_type = mch_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", + mchid, get_dev_revision(SA_DEV_ROOT), mch_type); +} + +static void report_pch_info(void) +{ + int i; + pci_devfn_t dev = PCH_DEV_ESPI; + uint16_t espiid = get_dev_id(dev); + const char *pch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].espiid == espiid) { + pch_type = pch_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", + espiid, get_dev_revision(dev), pch_type); +} + +static void report_igd_info(void) +{ + int i; + pci_devfn_t dev = SA_DEV_IGD; + uint16_t igdid = get_dev_id(dev); + const char *igd_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(igd_table); i++) { + if (igd_table[i].igdid == igdid) { + igd_type = igd_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", + igdid, get_dev_revision(dev), igd_type); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_mch_info(); + report_pch_info(); + report_igd_info(); +} -- cgit v1.2.3