From 930fded5b7f50333179c71e0d1fcf1857862dfe0 Mon Sep 17 00:00:00 2001 From: Dinesh Gehlot Date: Fri, 24 Feb 2023 05:09:04 +0000 Subject: soc/intel/adl: Select CSE defined ME spec version for alderlake Alderlake based SoCs uses Intel's Management Engine (ME), version 16. This patch selects ME 16 specification defined at common code and removes alderlake SoC specific ME code and data structures. BUG=b:260309647 Test=Build verified for brya. Signed-off-by: Dinesh Gehlot Change-Id: Ib94e4662c735b1c31c8dfca1cfa881e6fa4070fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/73244 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Lean Sheng Tan --- src/soc/intel/alderlake/Makefile.inc | 1 - 1 file changed, 1 deletion(-) (limited to 'src/soc/intel/alderlake/Makefile.inc') diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index fa52efbc6f..943b158564 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -33,7 +33,6 @@ ramstage-y += fsp_params.c ramstage-y += graphics.c ramstage-y += hsphy.c ramstage-y += lockdown.c -ramstage-y += me.c ramstage-y += p2sb.c ramstage-y += pcie_rp.c ramstage-y += pmc.c -- cgit v1.2.3