From 292afef2fbb5eaf46dd3efa0c9a54c125f71ad1a Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 9 Sep 2020 13:34:18 +0530 Subject: soc/intel/alderlake/romstage: Do initial SoC commit till romstage List of changes: 1. Add required SoC programming till romstage 2. Include only required headers into include/soc 3. Add SA EDS document number and chapter number 4. Fill required FSP-M UPD to call FSP-M API Change-Id: I4473aed27363c22e92e66cc6770cb55aae83e75c Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/45192 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/Makefile.inc | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/soc/intel/alderlake/Makefile.inc') diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index cc37b6fd00..a0b0e36e46 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -1,8 +1,22 @@ ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE),y) +subdirs-y += romstage +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/tsc + bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c +bootblock-y += espi.c +bootblock-y += p2sb.c + +romstage-y += espi.c +romstage-y += meminit.c +romstage-y += reset.c CPPFLAGS_common += -I$(src)/soc/intel/alderlake CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include endif -- cgit v1.2.3