From d307d0d2fb69f960ba300e27937105135f1a1a9c Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Thu, 21 Jul 2022 20:45:32 +0530 Subject: soc/soc/intel: Add UFS device with ref-clk-freq property UFS storage devices require the bRefClkFreq attribute to be set to operate correctly in high speed mode. The correct value is determined by what the SoC / board supports. For the ADL UFS controller, it is 19.2 MHz. a) Introduce a new ACPI property "ref-clk-freq". b) Add support to configure this property using an SoC Kconfig. Kernel patch: https://web.archive.org/web/20220801060732/https://lore.kernel.org/all/ 20220715210230.1.I365d113d275117dee8fd055ce4fc7e6aebd0bce9@changeid/ BUG=b:238262674 TEST=Build,boot Nirwen and dump SSDT entries and check that the kernel correctly parses ref-clk-freq as 19.2 MHz. Scope (\_SB.PCI0) { Device (UFS) { Name (_ADR, 0x0000000000120007) // _ADR: Address Name (_DDN, "UFS Controller") // _DDN: DOS Device Name Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "ref-clk-freq", 0x0124F800 } } }) } } Signed-off-by: Meera Ravindranath Signed-off-by: Reka Norman Change-Id: I80c338a8a61f161b0feb6c5a3ca00cf5e0cfb36c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66051 Tested-by: build bot (Jenkins) Reviewed-by: Ronak Kanabar Reviewed-by: Eric Lai --- src/soc/intel/alderlake/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/alderlake/Kconfig') diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index af1a04934c..5a6df8d758 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -295,6 +295,10 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ config CPU_XTAL_HZ default 38400000 +config SOC_INTEL_UFS_CLK_FREQ_HZ + int + default 19200000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 -- cgit v1.2.3