From 3c46371a514114aab744b86b1098dc27ebe891df Mon Sep 17 00:00:00 2001 From: John Zhao Date: Mon, 10 Jan 2022 15:49:37 -0800 Subject: soc/intel: Abstract the common block API for TCSS registers access The existing TCSS registers access is through the REGBAR. There will be future platforms which access the TCSS registers through the Sideband interface. This change abstracts the common block API for TCSS access. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao Change-Id: I3e2696b117af24412d73b257f470efc40caa5022 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60989 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai Reviewed-by: Subrata Banik --- src/soc/intel/alderlake/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/alderlake/Kconfig') diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index ac8c2e3843..89d0c93791 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -87,6 +87,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_TCSS + select SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_REGBAR select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE -- cgit v1.2.3