From 191bd827344302561c2aa900e5e5ecdd088c5888 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 21 Nov 2020 19:30:57 +0530 Subject: soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE According to the latest Alderlake Platform FSP Integration Guide, the minimum amount of stack needed for FSP-M is 512KiB. Change DCACHE_RAM_SIZE and DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined empirically). TEST=Able to pass FSP-M MRC training on LPDDR5 SKU without any hang. Change-Id: Ic831ca9110a15fdb48ad31a7db396740811bf0f2 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/47837 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/soc/intel/alderlake/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/alderlake/Kconfig') diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 0db8e1ceb2..0aab3c582f 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -70,18 +70,18 @@ config DCACHE_RAM_BASE default 0xfef00000 config DCACHE_RAM_SIZE - default 0x80000 + default 0xc0000 help The size of the cache-as-ram region required during bootblock and/or romstage. config DCACHE_BSP_STACK_SIZE hex - default 0x40400 + default 0x80400 help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be - sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement + sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement (~1KiB). config FSP_TEMP_RAM_SIZE -- cgit v1.2.3