From 092813a50ce4198d622daa809181216b6ffd1bd4 Mon Sep 17 00:00:00 2001
From: Tim Wawrzynczak <twawrzynczak@chromium.org>
Date: Tue, 24 Nov 2020 13:48:56 -0700
Subject: soc/intel/alderlake: Add initial chipset.cb

Similar to the chipset.cb for TGL, this patch gives alias names to all
of the published PCI devices.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6576ef4237c1fc8439795ad5b64b1840504edf73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48009
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/soc/intel/alderlake/Kconfig')

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 0aab3c582f..7e693cb373 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -92,6 +92,10 @@ config FSP_TEMP_RAM_SIZE
 	  Refer to Platform FSP integration guide document to know
 	  the exact FSP requirement for Heap setup.
 
+config CHIPSET_DEVICETREE
+	string
+	default "soc/intel/alderlake/chipset.cb"
+
 config IFD_CHIPSET
 	string
 	default "adl"
-- 
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