From 7271e23ec296b09420b72861e0d272ecbb94d2ca Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Fri, 9 Jan 2015 16:55:36 -0800 Subject: pistachio: report UART register width Pistachio UART closely matches 8250, the only difference is that its register file is mapped to a 32 bit bus. Provide a function to report register with so that the Coreboot table entry gets correct value. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board Change-Id: Icd72b115b4f339800d6c8b210a6617398232f806 Signed-off-by: Patrick Georgi Original-Commit-Id: e1dc4156949b20efafbca2c19ff424436a400087 Original-Change-Id: Icafb014af338e05bbf1044b791683733685ffab3 Original-Signed-off-by: Vadim Bendebury Original-Reviewed-on: https://chromium-review.googlesource.com/240028 Original-Reviewed-by: Ionela Voinescu Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/9740 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/imgtec/pistachio/uart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/imgtec') diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c index ff91459d87..ee5da57a37 100644 --- a/src/soc/imgtec/pistachio/uart.c +++ b/src/soc/imgtec/pistachio/uart.c @@ -179,7 +179,7 @@ void uart_fill_lb(void *data) serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); - serial.regwidth = 1; + serial.regwidth = 1 << UART_SHIFT; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); -- cgit v1.2.3