From 3218e794ba567ee7b51f2206e01f86f1d9358358 Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Sun, 1 Nov 2015 16:36:35 +0000 Subject: imgtec/pistachio: memlayout: update GRAM size GRAM is 421056 bytes. The end of the SRAM region (GRAM plays the role of SRAM) was placed at a 4K aligned address, resulting in a size of 408KB. Change-Id: I9fa32ab818d600e7447bcac895e4b8c438f2f99d Signed-off-by: Ionela Voinescu Reviewed-on: https://review.coreboot.org/12772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Alexandru Gagniuc --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/imgtec') diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index a0b48b2e6d..c84de40031 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -39,7 +39,7 @@ SECTIONS ROMSTAGE(0x1a005000, 40K) VBOOT2_WORK(0x1a00f000, 12K) PRERAM_CBFS_CACHE(0x1a012000, 56K) - SRAM_END(0x1a020000) + SRAM_END(0x1a066000) /* Bootblock executes out of KSEG0 and sets up the identity mapping. * This is identical to SRAM above, and thus also limited 64K and -- cgit v1.2.3