From fdce680759be398535c40d2f692f36e94e21f86e Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Tue, 17 Feb 2015 18:28:34 +0000 Subject: pistachio: implement clock setup for I2C0 BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; I2C0 clock is set up properly. BRANCH=none Change-Id: I15ffc5f7d8e8aadfc3cd249284bc492d0d13d9a1 Signed-off-by: Stefan Reinauer Original-Commit-Id: 6404ab6ad12ea1579eaf5ae55a9eddd9bd9f96e2 Original-Change-Id: Iafdf492291b47f0088f3b5e621d630b8d21ab106 Original-Signed-off-by: Ionela Voinescu Original-Reviewed-on: https://chromium-review.googlesource.com/250450 Original-Reviewed-by: David Hendricks Reviewed-on: http://review.coreboot.org/9673 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/imgtec/pistachio/include/soc/clocks.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/imgtec/pistachio/include') diff --git a/src/soc/imgtec/pistachio/include/soc/clocks.h b/src/soc/imgtec/pistachio/include/soc/clocks.h index f57d43d89e..81b640ebbd 100644 --- a/src/soc/imgtec/pistachio/include/soc/clocks.h +++ b/src/soc/imgtec/pistachio/include/soc/clocks.h @@ -28,6 +28,7 @@ int mips_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback); void system_clk_setup(u8 divider); void mips_clk_setup(u8 divider1, u8 divider2); void uart1_clk_setup(u8 divider1, u16 divider2); +void i2c0_clk_setup(u8 divider1, u16 divider2); int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel); void rom_clk_setup(u8 divider); void eth_clk_setup(u8 mux, u8 divider); -- cgit v1.2.3