From b3f666b252a7057a49f24b239e7f6c4ffd4f3350 Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Sun, 18 Jan 2015 22:37:11 +0000 Subject: urara: Configure clocks and MFIOs Set elements: - UART1 clock dividers and MFIOs - SPIM1 clock dividers and MFIOs - USB clock dividers - System clock divider - System PLL - MIPS CPU PLL BUG=chrome-os-partner:31438 TEST=tested on Pisachio bring up board; UART, SPI NOR, SPI NAND, and USB have proper functionality. BRANCH=none Change-Id: Ib01186a652fd59295a4cafc3ca99b94aa9564f74 Signed-off-by: Stefan Reinauer Original-Commit-Id: 65e68d82f34bb40ef3cfb397ecf5df0c83201151 Original-Change-Id: Ia2c31bbbfc020dc4fd71c72b877414adfdfc42a8 Original-Signed-off-by: Ionela Voinescu Original-Reviewed-on: https://chromium-review.googlesource.com/241423 Original-Reviewed-by: David Hendricks Reviewed-on: http://review.coreboot.org/9662 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/imgtec/pistachio/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/imgtec/pistachio/Makefile.inc') diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc index fdeba0cc01..6dc18f3b5e 100644 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ b/src/soc/imgtec/pistachio/Makefile.inc @@ -20,6 +20,7 @@ # # We enable CBFS_SPI_WRAPPER for Pistachio targets. +bootblock-y += clocks.c bootblock-y += spi.c romstage-y += spi.c ramstage-y += spi.c -- cgit v1.2.3