From d0c6797e796af155cd435ed344958dbb9c418a86 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 17 Apr 2018 13:47:55 +0200 Subject: soc/cavium: Add PCI support * Add support for secure/unsecure split * Use MMCONF to access devices in domain0 * Program MSIX vectors to fix a crash in GNU/Linux Tested on Cavium CN81XX_EVB. All PCI devices are visible. Change-Id: I881f38a26a165e6bd965fcd73547473b5e32d4b0 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/25750 Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- src/soc/cavium/common/pci/chip.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 src/soc/cavium/common/pci/chip.h (limited to 'src/soc/cavium/common') diff --git a/src/soc/cavium/common/pci/chip.h b/src/soc/cavium/common/pci/chip.h new file mode 100644 index 0000000000..0d0d33f59d --- /dev/null +++ b/src/soc/cavium/common/pci/chip.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018-present Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_CAVIUM_COMMON_PCI_CHIP_H +#define __SOC_CAVIUM_COMMON_PCI_CHIP_H + +struct soc_cavium_common_pci_config { + /** + * Mark the PCI device as secure. + * It will be visible from EL3, but hidden in EL2-0. + */ + u8 secure; +}; + +#endif /* __SOC_CAVIUM_COMMON_PCI_CHIP_H */ -- cgit v1.2.3