From 8cbd569f74d8929387730e45b0d6e993b1365c02 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Fri, 1 Dec 2017 20:49:48 -0800 Subject: cavium: Add CN81xx SoC and eval board support This adds Cavium CN81xx SoC and SFF EVB files. Code is based off of Cavium's Octeon-TX SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK BDK coreboot differences: bootblock: - Get rid of BDK header - Add Kconfig for link address - Move CAR setup code into assembly - Move unaligned memory access enable into assembly - Implement custom bootblock entry function - Add CLIB and CSIB blobs romstage: - Use minimal DRAM init only devicetree: - Convert FTD to static C file containing key value pairs Tested on CN81xx: - Boots to payload - Tested with GNU/Linux 4.16.3 - All hardware is usable (after applying additional commits) Implemented in future commits: - Vboot integration - MMU suuport - L2 Cache handling - ATF from external repo - Devicetree patching - Extended DRAM testing - UART init Not working: - Booting a payload - Booting upstream ATF TODO: - Configuration straps Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688 Signed-off-by: David Hendricks Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/23037 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/soc/cavium/common/Kconfig | 12 ++ src/soc/cavium/common/Makefile.inc | 58 +++++++++ src/soc/cavium/common/bdk-coreboot.c | 130 +++++++++++++++++++++ src/soc/cavium/common/bl31_plat_params.c | 32 +++++ src/soc/cavium/common/bootblock.c | 68 +++++++++++ src/soc/cavium/common/cbmem.c | 26 +++++ .../cavium/common/include/soc/bl31_plat_params.h | 25 ++++ src/soc/cavium/common/include/soc/bootblock.h | 29 +++++ src/soc/cavium/common/include/soc/sysreg.h | 65 +++++++++++ src/soc/cavium/common/rom_clib_s_nbl1fw.bin.hex | 16 +++ src/soc/cavium/common/rom_csib_s_nbl1fw.bin.hex | 16 +++ 11 files changed, 477 insertions(+) create mode 100644 src/soc/cavium/common/Kconfig create mode 100644 src/soc/cavium/common/Makefile.inc create mode 100644 src/soc/cavium/common/bdk-coreboot.c create mode 100644 src/soc/cavium/common/bl31_plat_params.c create mode 100644 src/soc/cavium/common/bootblock.c create mode 100644 src/soc/cavium/common/cbmem.c create mode 100644 src/soc/cavium/common/include/soc/bl31_plat_params.h create mode 100644 src/soc/cavium/common/include/soc/bootblock.h create mode 100644 src/soc/cavium/common/include/soc/sysreg.h create mode 100644 src/soc/cavium/common/rom_clib_s_nbl1fw.bin.hex create mode 100644 src/soc/cavium/common/rom_csib_s_nbl1fw.bin.hex (limited to 'src/soc/cavium/common') diff --git a/src/soc/cavium/common/Kconfig b/src/soc/cavium/common/Kconfig new file mode 100644 index 0000000000..1161ac2263 --- /dev/null +++ b/src/soc/cavium/common/Kconfig @@ -0,0 +1,12 @@ +config SOC_CAVIUM_COMMON + bool + default n + select BOOTBLOCK_CUSTOM + select CAVIUM_BDK + select FLATTENED_DEVICE_TREE +# FIXME: No Cavium support in ATF +# select ARM64_USE_ARM_TRUSTED_FIRMWARE + +if SOC_CAVIUM_COMMON + +endif diff --git a/src/soc/cavium/common/Makefile.inc b/src/soc/cavium/common/Makefile.inc new file mode 100644 index 0000000000..89add5f3f1 --- /dev/null +++ b/src/soc/cavium/common/Makefile.inc @@ -0,0 +1,58 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2017-present Facebook, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_SOC_CAVIUM_COMMON),y) + +CFLAGS_arm64 += -Wstack-usage=8192 + +bootblock-$(CONFIG_BOOTBLOCK_CUSTOM) += bootblock.c + +################################################################################ +# romstage + +romstage-y += cbmem.c +romstage-y += bdk-coreboot.c + +################################################################################ +# ramstage + +ramstage-y += cbmem.c +ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c + +CPPFLAGS_common += -Isrc/soc/cavium/common/include + +ROM_HEADER_BIN := $(objgenerated)/rom_header.bin +ROM_HEADER_SOURCES += rom_clib_s_nbl1fw +ROM_HEADER_SOURCES += rom_csib_s_nbl1fw + +ROM_HEADER_DEPS := $(foreach f, $(ROM_HEADER_SOURCES), src/soc/cavium/common/$(f).bin.hex) + +# Include ROM header +$(ROM_HEADER_BIN): $(ROM_HEADER_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(ROM_HEADER_BIN) + @printf " GEN $(subst $(obj)/,,$(@))\n" + dd if=/dev/zero ibs=1 count=$$(($(shell stat --printf="%s" $(objcbfs)/bootblock.raw.bin) + 0x10000)) of=$@ status=none + # Insert CLIB at 0x0 and CSIB at 0x100 + dd if=$(ROM_HEADER_BIN) of=$@ bs=1 seek=0 conv=notrunc status=none + # Insert bootblock at 0x10000 + dd if=$(objcbfs)/bootblock.raw.bin of=$@ bs=1 seek=$$((0x10000)) conv=notrunc status=none + +endif diff --git a/src/soc/cavium/common/bdk-coreboot.c b/src/soc/cavium/common/bdk-coreboot.c new file mode 100644 index 0000000000..ff30edfa79 --- /dev/null +++ b/src/soc/cavium/common/bdk-coreboot.c @@ -0,0 +1,130 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017-present Facebook, Inc. + * Copyright 2003-2017 Cavium Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * This file consists of data imported from bdk-config.c + */ +// coreboot +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// BDK +#include +#include +#include +#include + +/** + * Do a twsi read from a 7 bit device address using an (optional) + * internal address. Up to 4 bytes can be read at a time. + * + * @param twsi_id which TWSI bus to use + * @param dev_addr Device address (7 bit) + * @param internal_addr + * Internal address. Can be 0, 1 or 2 bytes in width + * @param num_bytes Number of data bytes to read (1-4) + * @param ia_width_bytes + * Internal address size in bytes (0, 1, or 2) + * + * @return Read data, or -1 on failure + */ +int64_t bdk_twsix_read_ia(bdk_node_t node, int twsi_id, uint8_t dev_addr, + uint16_t internal_addr, int num_bytes, + int ia_width_bytes) +{ + struct i2c_msg seg[2]; + u32 buf; + + assert (num_bytes < 5); + assert (ia_width_bytes < 3); + + seg[0].flags = 0; + seg[0].slave = dev_addr; + seg[0].buf = (u8 *)&internal_addr; + seg[0].len = ia_width_bytes; + seg[1].flags = I2C_M_RD; + seg[1].slave = dev_addr; + seg[1].buf = (u8 *)&buf; + seg[1].len = num_bytes; + + if (i2c_transfer(twsi_id, seg, ARRAY_SIZE(seg)) < 0) + return -1; + + return cpu_to_be32(buf); +} + +/** + * Write 1-8 bytes to a TWSI device using an internal address. + * + * @param twsi_id which TWSI interface to use + * @param dev_addr TWSI device address (7 bit only) + * @param internal_addr + * TWSI internal address (0, 8, or 16 bits) + * @param num_bytes Number of bytes to write (1-8) + * @param ia_width_bytes + * internal address width, in bytes (0, 1, 2) + * @param data Data to write. Data is written MSB first on the twsi bus, and + * only the lower num_bytes bytes of the argument are valid. (If + * a 2 byte write is done, only the low 2 bytes of the argument is + * used. + * + * @return Zero on success, -1 on error + */ +int bdk_twsix_write_ia(bdk_node_t node, int twsi_id, uint8_t dev_addr, + uint16_t internal_addr, int num_bytes, + int ia_width_bytes, uint64_t data) +{ + struct i2c_msg seg; + u8 buf[10]; + + assert (num_bytes <= 8); + assert (ia_width_bytes < 3); + + memcpy(buf, &internal_addr, ia_width_bytes); + memcpy(&buf[ia_width_bytes], &data, num_bytes); + + seg.flags = 0; + seg.slave = dev_addr; + seg.buf = buf; + seg.len = num_bytes + ia_width_bytes; + + return platform_i2c_transfer(twsi_id, &seg, 1); +} + +void bdk_watchdog_set(unsigned int timeout_ms) +{ + watchdog_set(0, timeout_ms); +} + +void bdk_watchdog_poke(void) +{ + watchdog_poke(0); +} + +void bdk_watchdog_disable(void) +{ + watchdog_disable(0); +} + +int bdk_watchdog_is_running(void) +{ + return watchdog_is_running(0); +} diff --git a/src/soc/cavium/common/bl31_plat_params.c b/src/soc/cavium/common/bl31_plat_params.c new file mode 100644 index 0000000000..583eac8059 --- /dev/null +++ b/src/soc/cavium/common/bl31_plat_params.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include + +static struct bl31_plat_param *plat_params; + +void register_bl31_param(struct bl31_plat_param *param) +{ + param->next = plat_params; + plat_params = param; +} + +void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) +{ + return plat_params; +} diff --git a/src/soc/cavium/common/bootblock.c b/src/soc/cavium/common/bootblock.c new file mode 100644 index 0000000000..c61a8d7dc1 --- /dev/null +++ b/src/soc/cavium/common/bootblock.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018-present Facebook, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_OPTIONAL_REGION(timestamp); + +__attribute__((weak)) void bootblock_mainboard_early_init(void) { /* no-op */ } +__attribute__((weak)) void bootblock_soc_early_init(void) { /* do nothing */ } +__attribute__((weak)) void bootblock_soc_init(void) { /* do nothing */ } +__attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ } + + +/* C code entry point for the boot block */ +void bootblock_main(const uint64_t reg_x0, + const uint64_t reg_x1, + const uint64_t reg_pc) +{ + uint64_t base_timestamp = 0; + + init_timer(); + + if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)) + base_timestamp = timestamp_get(); + + /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */ + if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && _timestamp_size > 0) + timestamp_init(base_timestamp); + + bootblock_soc_early_init(); + bootblock_mainboard_early_init(); + + if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + console_init(); + exception_init(); + + if (reg_x0) + printk(BIOS_ERR, + "BOOTBLOCK: RST Boot Failure Code %lld\n", + reg_x0); + + printk(BIOS_DEBUG, "BOOTBLOCK: FDT 0x%llX\n", reg_x1); + } + + bootblock_soc_init(); + bootblock_mainboard_init(); + + run_romstage(); +} diff --git a/src/soc/cavium/common/cbmem.c b/src/soc/cavium/common/cbmem.c new file mode 100644 index 0000000000..401f8b2a65 --- /dev/null +++ b/src/soc/cavium/common/cbmem.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +void *cbmem_top(void) +{ + return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + MAX_DRAM_ADDRESS); +} diff --git a/src/soc/cavium/common/include/soc/bl31_plat_params.h b/src/soc/cavium/common/include/soc/bl31_plat_params.h new file mode 100644 index 0000000000..3407e90c07 --- /dev/null +++ b/src/soc/cavium/common/include/soc/bl31_plat_params.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __BL31_PLAT_PARAMS_H__ +#define __BL31_PLAT_PARAMS_H__ + +// FIXME: use correct path one ATF is upstream +#include + +void register_bl31_param(struct bl31_plat_param *param); + +#endif/* __BL31_PLAT_PARAMS_H__ */ diff --git a/src/soc/cavium/common/include/soc/bootblock.h b/src/soc/cavium/common/include/soc/bootblock.h new file mode 100644 index 0000000000..040c5a3a67 --- /dev/null +++ b/src/soc/cavium/common/include/soc/bootblock.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018-present Facebook, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_ +#define SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_ + +void bootblock_mainboard_early_init(void); +void bootblock_soc_early_init(void); +void bootblock_soc_init(void); +void bootblock_mainboard_init(void); + +void bootblock_main(const uint64_t reg_x0, + const uint64_t reg_x1, + const uint64_t reg_pc); + + +#endif /* SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_ */ diff --git a/src/soc/cavium/common/include/soc/sysreg.h b/src/soc/cavium/common/include/soc/sysreg.h new file mode 100644 index 0000000000..655fe09cb6 --- /dev/null +++ b/src/soc/cavium/common/include/soc/sysreg.h @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018-present Facebook, Inc. + * Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_CAVIUM_COMMON_INCLUDE_SOC_SYSREG_H +#define __SOC_CAVIUM_COMMON_INCLUDE_SOC_SYSREG_H + +/* TODO: add CVMCTL_EL1 */ + +#define AP_CVMMEMCTL0_EL1_NODE_SHIFT 61 +#define AP_CVMMEMCTL0_EL1_NODE_MASK 0x3 +#define AP_CVMMEMCTL0_EL1_STEXFAILCNT_SHIFT 58 +#define AP_CVMMEMCTL0_EL1_STEXFAILCNT_MASK 0x7 +#define AP_CVMMEMCTL0_EL1_WFELDEX1DIS (1 << 57) +#define AP_CVMMEMCTL0_EL1_STLSTALLFORCE (1 << 56) +#define AP_CVMMEMCTL0_EL1_DMBSTALLFORCE (1 << 55) +#define AP_CVMMEMCTL0_EL1_TLBINOPDIS (1 << 54) +#define AP_CVMMEMCTL0_EL1_TLBIICFLUSH (1 << 53) +#define AP_CVMMEMCTL0_EL1_GSYNCTO_SHIFT 48 +#define AP_CVMMEMCTL0_EL1_GSYNCTO_MASK 0x1f +#define AP_CVMMEMCTL0_EL1_UTLBFILLBYPDIS (1 << 47) +#define AP_CVMMEMCTL0_EL1_TLBIALL (1 << 46) +#define AP_CVMMEMCTL0_EL1_WBFDSBFLUSHALL (1 << 45) +#define AP_CVMMEMCTL0_EL1_WBFDMBFLUSHNEXT (1 << 44) +#define AP_CVMMEMCTL0_EL1_STEXL2CFORCE (1 << 43) +#define AP_CVMMEMCTL0_EL1_WCUMISSFORCE (1 << 41) +#define AP_CVMMEMCTL0_EL1_REPLAYPREFDIS (1 << 40) +#define AP_CVMMEMCTL0_EL1_ZVAL2CDIS (1 << 39) +#define AP_CVMMEMCTL0_EL1_LDIL2CDIS (1 << 38) +#define AP_CVMMEMCTL0_EL1_DVCA47 (1 << 37) +#define AP_CVMMEMCTL0_EL1_STPREFDIS (1 << 36) +#define AP_CVMMEMCTL0_EL1_LDPREFDIS (1 << 35) +#define AP_CVMMEMCTL0_EL1_WFILDEXDIS (1 << 34) +#define AP_CVMMEMCTL0_EL1_WFITO_SHIFT 31 +#define AP_CVMMEMCTL0_EL1_WFITO_MASK 0x7 +#define AP_CVMMEMCTL0_EL1_RBFSHORTTO_SHIFT 26 +#define AP_CVMMEMCTL0_EL1_RBFSHORTTO_MASK 0x1f +#define AP_CVMMEMCTL0_EL1_RBFTO_SHIFT 21 +#define AP_CVMMEMCTL0_EL1_RBFTO_MASK 0x1f +#define AP_CVMMEMCTL0_EL1_WBFALLBARRIER (1 << 20) +#define AP_CVMMEMCTL0_EL1_WBFNOMERGE (1 << 19) +#define AP_CVMMEMCTL0_EL1_WBFTONSHENA (1 << 18) +#define AP_CVMMEMCTL0_EL1_WBFTOMRGCLRENA (1 << 17) +#define AP_CVMMEMCTL0_EL1_WBFTO_SHIFT 12 +#define AP_CVMMEMCTL0_EL1_WBFTO_MASK 0x1f +#define AP_CVMMEMCTL0_EL1_WBFTHRESH_SHIFT 7 +#define AP_CVMMEMCTL0_EL1_WBFTHRESH_MASK 0x1f +#define AP_CVMMEMCTL0_EL1_UTLBENTRIESM1_SHIFT 2 +#define AP_CVMMEMCTL0_EL1_UTLBENTRIESM1_MASK 0x1f +#define AP_CVMMEMCTL0_EL1_CCLKFORCE (1 << 1) +#define AP_CVMMEMCTL0_EL1_MCLKFORCE (1 << 0) + +#endif /* __SOC_CAVIUM_COMMON_INCLUDE_SOC_SYSREG_H */ diff --git a/src/soc/cavium/common/rom_clib_s_nbl1fw.bin.hex b/src/soc/cavium/common/rom_clib_s_nbl1fw.bin.hex new file mode 100644 index 0000000000..231c6a60b1 --- /dev/null +++ b/src/soc/cavium/common/rom_clib_s_nbl1fw.bin.hex @@ -0,0 +1,16 @@ +43 56 4d 5f 43 4c 49 42 00 00 00 00 00 00 00 00 +00 00 02 00 00 00 00 00 00 00 03 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/cavium/common/rom_csib_s_nbl1fw.bin.hex b/src/soc/cavium/common/rom_csib_s_nbl1fw.bin.hex new file mode 100644 index 0000000000..f7a2021aaf --- /dev/null +++ b/src/soc/cavium/common/rom_csib_s_nbl1fw.bin.hex @@ -0,0 +1,16 @@ +43 56 4d 5f 43 53 49 42 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- cgit v1.2.3