From 8cbd569f74d8929387730e45b0d6e993b1365c02 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Fri, 1 Dec 2017 20:49:48 -0800 Subject: cavium: Add CN81xx SoC and eval board support This adds Cavium CN81xx SoC and SFF EVB files. Code is based off of Cavium's Octeon-TX SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK BDK coreboot differences: bootblock: - Get rid of BDK header - Add Kconfig for link address - Move CAR setup code into assembly - Move unaligned memory access enable into assembly - Implement custom bootblock entry function - Add CLIB and CSIB blobs romstage: - Use minimal DRAM init only devicetree: - Convert FTD to static C file containing key value pairs Tested on CN81xx: - Boots to payload - Tested with GNU/Linux 4.16.3 - All hardware is usable (after applying additional commits) Implemented in future commits: - Vboot integration - MMU suuport - L2 Cache handling - ATF from external repo - Devicetree patching - Extended DRAM testing - UART init Not working: - Booting a payload - Booting upstream ATF TODO: - Configuration straps Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688 Signed-off-by: David Hendricks Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/23037 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- .../cavium/common/include/soc/bl31_plat_params.h | 25 +++++++++ src/soc/cavium/common/include/soc/bootblock.h | 29 ++++++++++ src/soc/cavium/common/include/soc/sysreg.h | 65 ++++++++++++++++++++++ 3 files changed, 119 insertions(+) create mode 100644 src/soc/cavium/common/include/soc/bl31_plat_params.h create mode 100644 src/soc/cavium/common/include/soc/bootblock.h create mode 100644 src/soc/cavium/common/include/soc/sysreg.h (limited to 'src/soc/cavium/common/include') diff --git a/src/soc/cavium/common/include/soc/bl31_plat_params.h b/src/soc/cavium/common/include/soc/bl31_plat_params.h new file mode 100644 index 0000000000..3407e90c07 --- /dev/null +++ b/src/soc/cavium/common/include/soc/bl31_plat_params.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __BL31_PLAT_PARAMS_H__ +#define __BL31_PLAT_PARAMS_H__ + +// FIXME: use correct path one ATF is upstream +#include + +void register_bl31_param(struct bl31_plat_param *param); + +#endif/* __BL31_PLAT_PARAMS_H__ */ diff --git a/src/soc/cavium/common/include/soc/bootblock.h b/src/soc/cavium/common/include/soc/bootblock.h new file mode 100644 index 0000000000..040c5a3a67 --- /dev/null +++ b/src/soc/cavium/common/include/soc/bootblock.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018-present Facebook, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_ +#define SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_ + +void bootblock_mainboard_early_init(void); +void bootblock_soc_early_init(void); +void bootblock_soc_init(void); +void bootblock_mainboard_init(void); + +void bootblock_main(const uint64_t reg_x0, + const uint64_t reg_x1, + const uint64_t reg_pc); + + +#endif /* SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_ */ diff --git a/src/soc/cavium/common/include/soc/sysreg.h b/src/soc/cavium/common/include/soc/sysreg.h new file mode 100644 index 0000000000..655fe09cb6 --- /dev/null +++ b/src/soc/cavium/common/include/soc/sysreg.h @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018-present Facebook, Inc. + * Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_CAVIUM_COMMON_INCLUDE_SOC_SYSREG_H +#define __SOC_CAVIUM_COMMON_INCLUDE_SOC_SYSREG_H + +/* TODO: add CVMCTL_EL1 */ + +#define AP_CVMMEMCTL0_EL1_NODE_SHIFT 61 +#define AP_CVMMEMCTL0_EL1_NODE_MASK 0x3 +#define AP_CVMMEMCTL0_EL1_STEXFAILCNT_SHIFT 58 +#define AP_CVMMEMCTL0_EL1_STEXFAILCNT_MASK 0x7 +#define AP_CVMMEMCTL0_EL1_WFELDEX1DIS (1 << 57) +#define AP_CVMMEMCTL0_EL1_STLSTALLFORCE (1 << 56) +#define AP_CVMMEMCTL0_EL1_DMBSTALLFORCE (1 << 55) +#define AP_CVMMEMCTL0_EL1_TLBINOPDIS (1 << 54) +#define AP_CVMMEMCTL0_EL1_TLBIICFLUSH (1 << 53) +#define AP_CVMMEMCTL0_EL1_GSYNCTO_SHIFT 48 +#define AP_CVMMEMCTL0_EL1_GSYNCTO_MASK 0x1f +#define AP_CVMMEMCTL0_EL1_UTLBFILLBYPDIS (1 << 47) +#define AP_CVMMEMCTL0_EL1_TLBIALL (1 << 46) +#define AP_CVMMEMCTL0_EL1_WBFDSBFLUSHALL (1 << 45) +#define AP_CVMMEMCTL0_EL1_WBFDMBFLUSHNEXT (1 << 44) +#define AP_CVMMEMCTL0_EL1_STEXL2CFORCE (1 << 43) +#define AP_CVMMEMCTL0_EL1_WCUMISSFORCE (1 << 41) +#define AP_CVMMEMCTL0_EL1_REPLAYPREFDIS (1 << 40) +#define AP_CVMMEMCTL0_EL1_ZVAL2CDIS (1 << 39) +#define AP_CVMMEMCTL0_EL1_LDIL2CDIS (1 << 38) +#define AP_CVMMEMCTL0_EL1_DVCA47 (1 << 37) +#define AP_CVMMEMCTL0_EL1_STPREFDIS (1 << 36) +#define AP_CVMMEMCTL0_EL1_LDPREFDIS (1 << 35) +#define AP_CVMMEMCTL0_EL1_WFILDEXDIS (1 << 34) +#define AP_CVMMEMCTL0_EL1_WFITO_SHIFT 31 +#define AP_CVMMEMCTL0_EL1_WFITO_MASK 0x7 +#define AP_CVMMEMCTL0_EL1_RBFSHORTTO_SHIFT 26 +#define AP_CVMMEMCTL0_EL1_RBFSHORTTO_MASK 0x1f +#define AP_CVMMEMCTL0_EL1_RBFTO_SHIFT 21 +#define AP_CVMMEMCTL0_EL1_RBFTO_MASK 0x1f +#define AP_CVMMEMCTL0_EL1_WBFALLBARRIER (1 << 20) +#define AP_CVMMEMCTL0_EL1_WBFNOMERGE (1 << 19) +#define AP_CVMMEMCTL0_EL1_WBFTONSHENA (1 << 18) +#define AP_CVMMEMCTL0_EL1_WBFTOMRGCLRENA (1 << 17) +#define AP_CVMMEMCTL0_EL1_WBFTO_SHIFT 12 +#define AP_CVMMEMCTL0_EL1_WBFTO_MASK 0x1f +#define AP_CVMMEMCTL0_EL1_WBFTHRESH_SHIFT 7 +#define AP_CVMMEMCTL0_EL1_WBFTHRESH_MASK 0x1f +#define AP_CVMMEMCTL0_EL1_UTLBENTRIESM1_SHIFT 2 +#define AP_CVMMEMCTL0_EL1_UTLBENTRIESM1_MASK 0x1f +#define AP_CVMMEMCTL0_EL1_CCLKFORCE (1 << 1) +#define AP_CVMMEMCTL0_EL1_MCLKFORCE (1 << 0) + +#endif /* __SOC_CAVIUM_COMMON_INCLUDE_SOC_SYSREG_H */ -- cgit v1.2.3