From b94ecc4e696cc63e2772657c915670c3fe057f5c Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 22 Feb 2019 12:05:16 +0100 Subject: soc/cavium/common: Make ecam0_get_bar_val common MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move ecam0_get_bar_val into the common folder and make it public. Compile it for romstage and ramstage. To be used by romstage PCI code. Tested on OpenCellular Elgon. Change-Id: I18b1ede56795bf8c1f9476592291b8ea610eccd4 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/31566 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Kyösti Mälkki --- src/soc/cavium/cn81xx/ecam0.c | 47 ++----------------------------------------- 1 file changed, 2 insertions(+), 45 deletions(-) (limited to 'src/soc/cavium/cn81xx') diff --git a/src/soc/cavium/cn81xx/ecam0.c b/src/soc/cavium/cn81xx/ecam0.c index 6747fa6ad1..0ce0c8f2fa 100644 --- a/src/soc/cavium/cn81xx/ecam0.c +++ b/src/soc/cavium/cn81xx/ecam0.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #define CAVM_PCCPF_XXX_VSEC_CTL 0x108 @@ -136,50 +137,6 @@ static void ecam0_fix_missing_devices(struct bus *link) } } -/** - * Get PCI BAR address from cavium specific extended capability. - * Use regular BAR if not found in extended capability space. - * - * @return The pyhsical address of the BAR, zero on error - */ -static uint64_t get_bar_val(struct device *dev, u8 bar) -{ - size_t cap_offset = pci_find_capability(dev, 0x14); - uint64_t h, l, ret = 0; - if (cap_offset) { - /* Found EA */ - u8 es, bei; - u8 ne = pci_read_config8(dev, cap_offset + 2) & 0x3f; - - cap_offset += 4; - while (ne) { - uint32_t dw0 = pci_read_config32(dev, cap_offset); - - es = dw0 & 7; - bei = (dw0 >> 4) & 0xf; - if (bei == bar) { - h = 0; - l = pci_read_config32(dev, cap_offset + 4); - if (l & 2) - h = pci_read_config32(dev, - cap_offset + 12); - ret = (h << 32) | (l & ~0xfull); - break; - } - cap_offset += (es + 1) * 4; - ne--; - } - } else { - h = 0; - l = pci_read_config32(dev, bar * 4 + PCI_BASE_ADDRESS_0); - if (l & 4) - h = pci_read_config32(dev, bar * 4 + PCI_BASE_ADDRESS_0 - + 4); - ret = (h << 32) | (l & ~0xfull); - } - return ret; -} - /** * pci_enable_msix - configure device's MSI-X capability structure * @dev: pointer to the pci_dev data structure of MSI-X device function @@ -237,7 +194,7 @@ static size_t ecam0_pci_enable_msix(struct device *dev, dev_path(dev)); return -1; } - bar = get_bar_val(dev, bar_idx); + bar = ecam0_get_bar_val(dev, bar_idx); if (!bar) { printk(BIOS_ERR, "ERROR: %s: Failed to find MSI-X bar\n", dev_path(dev)); -- cgit v1.2.3