From 52acef175e42374d463214427678e3e7828960c3 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 8 Aug 2018 12:46:18 +0200 Subject: soc/cavium/cn81xx: Fix minor things * Move cbmem.c to cn81xx folder * Store CBMEM below 4 GiB * Make sure CBMEM doesn't overlap with ATF scratchpad * Fix ATF scratchpad not marked as reserved due to wrong calculation * The scratchpad is the last 1 MiB at the end of DRAM. Tested on Cavium CN81xx EVB: The ATF scratchpad is now marked reserved and the configuration tables are located below 4 GiB. Linux still boots. Change-Id: Ibbc8b586f04bd6867c045f5546b32a77c057ac74 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/27955 Reviewed-by: Philipp Deppenwiese Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/cavium/cn81xx/Makefile.inc | 11 ++--------- src/soc/cavium/cn81xx/cbmem.c | 27 +++++++++++++++++++++++++++ src/soc/cavium/cn81xx/soc.c | 3 ++- 3 files changed, 31 insertions(+), 10 deletions(-) create mode 100644 src/soc/cavium/cn81xx/cbmem.c (limited to 'src/soc/cavium/cn81xx') diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc index 845ac34961..2179bc7ec8 100644 --- a/src/soc/cavium/cn81xx/Makefile.inc +++ b/src/soc/cavium/cn81xx/Makefile.inc @@ -39,16 +39,11 @@ romstage-y += timer.c romstage-y += spi.c romstage-y += uart.c romstage-$(CONFIG_DRIVERS_UART) += uart.c -romstage-< += cpu.c +romstage-y += cbmem.c romstage-y += sdram.c romstage-y += mmu.c -romstage-y += ../common/cbmem.c -# BDK coreboot interface -romstage-y += ../common/bdk-coreboot.c - - ################################################################################ # ramstage @@ -64,12 +59,10 @@ ramstage-y += soc.c ramstage-y += cpu.c ramstage-y += cpu_secondary.S ramstage-y += ecam0.c +ramstage-y += cbmem.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c -# BDK coreboot interface -ramstage-y += ../common/bdk-coreboot.c - BL31_MAKEARGS += PLAT=t81 M0_CROSS_COMPILE="$(CROSS_COMPILE_arm)" ENABLE_SPE_FOR_LOWER_ELS=0 CPPFLAGS_common += -Isrc/soc/cavium/cn81xx/include diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c new file mode 100644 index 0000000000..397fd263d7 --- /dev/null +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +void *cbmem_top(void) +{ + /* Make sure not to overlap with reserved ATF scratchpad */ + return (void *)min((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB, + 4ULL * GiB); +} diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index b575ca4391..8efcb1374c 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -309,7 +309,8 @@ void bootmem_platform_add_ranges(void) BM_MEM_RESERVED); /* Scratchpad for ATF SATA quirks */ - bootmem_add_range(sdram_size_mb() * KiB, 1 * MiB, BM_MEM_RESERVED); + bootmem_add_range((sdram_size_mb() - 1) * MiB, 1 * MiB, + BM_MEM_RESERVED); } static void soc_read_resources(device_t dev) -- cgit v1.2.3