From de4410c51fe5c5113643663644dd635c917a7ab2 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 27 Mar 2018 12:01:40 +0200 Subject: soc/cavium: Apply additional devicetree fixups Depends on Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d Apply additional devicetree fixes: * Update SCLK from boot fuses * Updated REFCLKUAA from UART ref clock divider settings * Remove disabled PEM entries * Remove phandle to disabled PEM entries Fixes: * Linux console wrong baud rate once the PL011 driver is started. * thunderx-pem kernel module crash on disable PCIe ports. Tested on Cavium SoC. Change-Id: I7e8eefd913915a879dad28dfb7801a2018ed2985 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/25382 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/soc/cavium/cn81xx/include/soc/addressmap.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/cavium/cn81xx/include') diff --git a/src/soc/cavium/cn81xx/include/soc/addressmap.h b/src/soc/cavium/cn81xx/include/soc/addressmap.h index 392c93f1c1..f6983064fc 100644 --- a/src/soc/cavium/cn81xx/include/soc/addressmap.h +++ b/src/soc/cavium/cn81xx/include/soc/addressmap.h @@ -94,6 +94,8 @@ (0x87E090000000ULL + ((x) << 24)) : 0) /* PEM */ +#define PEM_PEMX_PF_BAR0(x) (0x87e0c0000000ULL + 0x1000000ULL * (x)) + /* SATA */ /* USB */ -- cgit v1.2.3