From 52acef175e42374d463214427678e3e7828960c3 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 8 Aug 2018 12:46:18 +0200 Subject: soc/cavium/cn81xx: Fix minor things * Move cbmem.c to cn81xx folder * Store CBMEM below 4 GiB * Make sure CBMEM doesn't overlap with ATF scratchpad * Fix ATF scratchpad not marked as reserved due to wrong calculation * The scratchpad is the last 1 MiB at the end of DRAM. Tested on Cavium CN81xx EVB: The ATF scratchpad is now marked reserved and the configuration tables are located below 4 GiB. Linux still boots. Change-Id: Ibbc8b586f04bd6867c045f5546b32a77c057ac74 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/27955 Reviewed-by: Philipp Deppenwiese Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/cavium/cn81xx/Makefile.inc | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) (limited to 'src/soc/cavium/cn81xx/Makefile.inc') diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc index 845ac34961..2179bc7ec8 100644 --- a/src/soc/cavium/cn81xx/Makefile.inc +++ b/src/soc/cavium/cn81xx/Makefile.inc @@ -39,16 +39,11 @@ romstage-y += timer.c romstage-y += spi.c romstage-y += uart.c romstage-$(CONFIG_DRIVERS_UART) += uart.c -romstage-< += cpu.c +romstage-y += cbmem.c romstage-y += sdram.c romstage-y += mmu.c -romstage-y += ../common/cbmem.c -# BDK coreboot interface -romstage-y += ../common/bdk-coreboot.c - - ################################################################################ # ramstage @@ -64,12 +59,10 @@ ramstage-y += soc.c ramstage-y += cpu.c ramstage-y += cpu_secondary.S ramstage-y += ecam0.c +ramstage-y += cbmem.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c -# BDK coreboot interface -ramstage-y += ../common/bdk-coreboot.c - BL31_MAKEARGS += PLAT=t81 M0_CROSS_COMPILE="$(CROSS_COMPILE_arm)" ENABLE_SPE_FOR_LOWER_ELS=0 CPPFLAGS_common += -Isrc/soc/cavium/cn81xx/include -- cgit v1.2.3