From a342f3937e7ce159fd170ab8cd26ba799a3bc9e4 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 17 Oct 2018 10:56:26 +0200 Subject: src: Remove unneeded whitespace Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/broadcom/cygnus/ddr_init.c | 140 ++++++++++++++++++------------- src/soc/broadcom/cygnus/phy_reg_access.c | 16 ++-- src/soc/broadcom/cygnus/usb.c | 2 +- 3 files changed, 90 insertions(+), 68 deletions(-) (limited to 'src/soc/broadcom') diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c index ff5dc87f78..e00ae917a5 100644 --- a/src/soc/broadcom/cygnus/ddr_init.c +++ b/src/soc/broadcom/cygnus/ddr_init.c @@ -70,70 +70,91 @@ void PRE_SRX(void) uint32_t readvalue = 0; // Disable low power receivers: bit 0 of the byte lane STATIC_PAD_CTL register - readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL); - reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL, ( readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); + readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL); + reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL, + (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); // Turn off ZQ_CAL drivers: bits 0,1, and 17 of the ZQ_CAL register (other bits 0 & 1 are set to 1) - readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL); - reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL, ( readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ))); + readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL); + reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL, + (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ))); // Byte lane 0 power up - readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); + readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); + reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, + (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); - readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & 0xffff800f)); + readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); + reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, + (readvalue & 0xffff800f)); - readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); + readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); + reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, + (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); // Byte lane 1 power up - readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); + readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); + reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, + (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); - readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & 0xffff800f)); + readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); + reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, + (readvalue & 0xffff800f)); - readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); + readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); + reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, + (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); // Turn on PHY_CONTROL AUTO_OEB C not required // Enable byte lane AUTO_DQ_RXENB_MODE: bits 18 and 19 of the byte lane IDLE_PAD_CONTROL C already set 180114c8: 000f000a printk(BIOS_INFO, "\n....PLL power up.\n"); - reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1< 0 ) { - printk(BIOS_INFO, "Running simple memory test ..... "); - i = simple_memory_test( - (void *)CONFIG_SHMOO_REUSE_MEMTEST_START, - CONFIG_SHMOO_REUSE_MEMTEST_LENGTH); - if (i) { - printk(BIOS_ERR, "failed!\n"); - return 1; - } - printk(BIOS_INFO, "OK\n"); - } + reg32_read(reg); /* Dummy read back */ + } + printk(BIOS_INFO, "done\n"); + + /* Perform memory test to see if the parameters work */ + if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) { + printk(BIOS_INFO, "Running simple memory test ..... "); + i = simple_memory_test((void *)CONFIG_SHMOO_REUSE_MEMTEST_START, + CONFIG_SHMOO_REUSE_MEMTEST_LENGTH); + if (i) { + printk(BIOS_ERR, "failed!\n"); + return 1; + } + printk(BIOS_INFO, "OK\n"); + } return 0; } @@ -1116,9 +1136,11 @@ static int clear_ddr(uint32_t offset, uint32_t size) unsigned long start; unsigned int i, val; - reg32_write((uint32_t *)DDR_BistConfig,reg32_read((uint32_t *)DDR_BistConfig) & ~0x1); + reg32_write((uint32_t *)DDR_BistConfig, + reg32_read((uint32_t *)DDR_BistConfig) & ~0x1); - for ( i = 0; i < 1000; i++); + for (i = 0; i < 1000; i++) + ; #if !defined(CONFIG_IPROC_P7) reg32_write((volatile uint32_t *)DDR_DENALI_CTL_213, 0x00FFFFFF); @@ -1377,10 +1399,10 @@ void ddr_init2(void) /* Wait for DDR PHY up */ for (i=0; i < 0x19000; i++) { val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); - if ( val != 0) { - printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val); + if (val != 0) { + printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val); break; /* DDR PHY is up */ - } + } } if (i == 0x19000) { @@ -1484,7 +1506,7 @@ void ddr_init2(void) /* Enable auto self-refresh */ reg32_set_bits((unsigned int *)DDR_DENALI_CTL_57, 0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R | - 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R ); + 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R); reg32_set_bits((unsigned int *)DDR_DENALI_CTL_58, DDR_AUTO_SELF_REFRESH_IDLE_COUNT << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R); @@ -1495,9 +1517,9 @@ void ddr_init2(void) /* Disable auto-self refresh */ reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_57, 0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R | - 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R ); + 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R); reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_58, - 0xff << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R ); + 0xff << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R); #endif /* Start the DDR */ @@ -1598,7 +1620,7 @@ void ddr_init2(void) /* SRX */ if (skip_shmoo) { - // Enter Self refresh (dummy) , to keep Denali happy + // Enter Self refresh (dummy), to keep Denali happy reg32_write((unsigned int *)DDR_DENALI_CTL_56, 0x0a050505); __udelay(200); diff --git a/src/soc/broadcom/cygnus/phy_reg_access.c b/src/soc/broadcom/cygnus/phy_reg_access.c index eb48133656..ea82dde4df 100644 --- a/src/soc/broadcom/cygnus/phy_reg_access.c +++ b/src/soc/broadcom/cygnus/phy_reg_access.c @@ -15,17 +15,17 @@ uint32 REGRD (uint32 address) { - volatile unsigned long data; + volatile unsigned long data; - data = (* (volatile uint32 *) ( ((uint32)GLOBAL_REG_RBUS_START) | (address))); - //printf("REGRD %08X=%08X\n", address, data); - return data; + data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))); + //printf("REGRD %08X=%08X\n", address, data); + return data; } uint32 REGWR (uint32 address, uint32 data) { - ((* (volatile uint32 *) ( ((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); - //printf("REGWR %08X=%08X\n", address, data); -// return SOC_E_NONE; - return 0; + ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); + //printf("REGWR %08X=%08X\n", address, data); + // return SOC_E_NONE; + return 0; } diff --git a/src/soc/broadcom/cygnus/usb.c b/src/soc/broadcom/cygnus/usb.c index d95efd1a87..5b93604412 100644 --- a/src/soc/broadcom/cygnus/usb.c +++ b/src/soc/broadcom/cygnus/usb.c @@ -47,7 +47,7 @@ struct bcm_phy_instance { struct phy *generic_phy; int port; - int host_mode; /* 1 - Host , 0 - device */ + int host_mode; /* 1 - Host, 0 - device */ int power; /* 1 -powered_on 0 -powered off */ struct regulator *vbus_supply; }; -- cgit v1.2.3