From a7cac0c21d85e651caaab2af7f8f1a7263e8abb9 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 19 Feb 2016 17:33:26 +0100 Subject: soc/*: fix uart's regwidth specification in cbtables coreboot passes information about the serial port implementation to payloads through a cbtables entry. We set the register width to 1 on most SoCs because that looked as good a default as any, but checking the uart structs they use, it's 4 for all of them. Change-Id: I9848f79737106dc32f864ca901c0bc48f489e6b8 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/13746 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/broadcom/cygnus/ns16550.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/broadcom/cygnus') diff --git a/src/soc/broadcom/cygnus/ns16550.c b/src/soc/broadcom/cygnus/ns16550.c index 4a4702aab8..71a4cb08ef 100644 --- a/src/soc/broadcom/cygnus/ns16550.c +++ b/src/soc/broadcom/cygnus/ns16550.c @@ -119,7 +119,7 @@ void uart_fill_lb(void *data) serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = (uintptr_t)regs; serial.baud = default_baudrate(); - serial.regwidth = 1; + serial.regwidth = 4; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); -- cgit v1.2.3