From f9270265360930a46387d617c18e55e67833edfb Mon Sep 17 00:00:00 2001 From: Chris Wang Date: Wed, 26 Apr 2023 19:48:05 +0800 Subject: soc/amd/mendocino: update FSP parameters for eDP power sequence adjustment Add UPD parameter for eDP power sequence adjustment. The edp_panel_t9_ms parameter is set for bloff to varybloff. BUG=b:271704149 BRANCH=Skyrim TEST=Build; Verify the UPD was pass to system integrated table. Signed-off-by: Chris Wang Change-Id: Id651c9cc4d6f4e27f6c78ca10ca12936d66ef43b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74789 Reviewed-by: Matt DeVillier Reviewed-by: Jason Glenesk Reviewed-by: Martin Roth Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) --- src/soc/amd/mendocino/chip.h | 2 ++ src/soc/amd/mendocino/fsp_m_params.c | 1 + 2 files changed, 3 insertions(+) (limited to 'src/soc/amd') diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 5eb7c41cb7..f161038e98 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -179,6 +179,8 @@ struct soc_amd_mendocino_config { /* Set for eDP power sequence adjustment timing T8 (from varybl to blon). */ uint8_t edp_panel_t8_ms; + /* Set for eDP power sequence adjustment timing T9 (from bloff to varybloff). */ + uint8_t edp_panel_t9_ms; }; diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c index cea26a9acd..6582a7cd50 100644 --- a/src/soc/amd/mendocino/fsp_m_params.c +++ b/src/soc/amd/mendocino/fsp_m_params.c @@ -171,6 +171,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable; mcfg->edp_panel_t8_ms = config->edp_panel_t8_ms; + mcfg->edp_panel_t9_ms = config->edp_panel_t9_ms; fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); -- cgit v1.2.3