From dea42e011a126c4fdc9ab62f6d6c449df4740f82 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 31 May 2021 20:26:16 +0300 Subject: cpu/x86/lapic: Replace LOCAL_APIC_ADDR references MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Note that there are assumptions about LAPIC MMIO location in both AMD and Intel sources in coreboot proper. Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194 Reviewed-by: Felix Held Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/data_fabric.c | 2 +- src/soc/amd/picasso/data_fabric.c | 2 +- src/soc/amd/stoneyridge/northbridge.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/soc/amd') diff --git a/src/soc/amd/cezanne/data_fabric.c b/src/soc/amd/cezanne/data_fabric.c index d603c8a132..1a0f9cb320 100644 --- a/src/soc/amd/cezanne/data_fabric.c +++ b/src/soc/amd/cezanne/data_fabric.c @@ -37,7 +37,7 @@ void data_fabric_set_mmio_np(void) int reg; uint32_t base, limit, ctrl; const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; - const uint32_t np_top = (LOCAL_APIC_ADDR - 1) >> D18F0_MMIO_SHIFT; + const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; data_fabric_print_mmio_conf(); diff --git a/src/soc/amd/picasso/data_fabric.c b/src/soc/amd/picasso/data_fabric.c index 700cb84d6b..b5949f028c 100644 --- a/src/soc/amd/picasso/data_fabric.c +++ b/src/soc/amd/picasso/data_fabric.c @@ -37,7 +37,7 @@ void data_fabric_set_mmio_np(void) int reg; uint32_t base, limit, ctrl; const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; - const uint32_t np_top = (LOCAL_APIC_ADDR - 1) >> D18F0_MMIO_SHIFT; + const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; data_fabric_print_mmio_conf(); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index a2e719b978..d80aeb2a09 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -340,7 +340,7 @@ void amd_initcpuio(void) /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */ base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE; - limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP; + limit = (ALIGN_DOWN(LAPIC_DEFAULT_BASE - 1, 64 * KiB) >> 8) | MMIO_NP; pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit); pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base); -- cgit v1.2.3