From c3ce09cdacde2472b6fc97504aca4f69ebc1b457 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Wed, 10 Feb 2021 16:25:53 +0100
Subject: soc/amd/cezanne/chip: set device operations for UART MMIO devices

Change-Id: I5df3a61741f05364e2c20725b0b85164b197dbdc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50484
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/cezanne/chip.c | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'src/soc/amd')

diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c
index 6e4df42bb9..ffd56de66d 100644
--- a/src/soc/amd/cezanne/chip.c
+++ b/src/soc/amd/cezanne/chip.c
@@ -6,6 +6,9 @@
 #include <types.h>
 #include "chip.h"
 
+/* Supplied by uart.c */
+extern struct device_operations cezanne_uart_mmio_ops;
+
 struct device_operations cpu_bus_ops = {
 	.read_resources	= noop_read_resources,
 	.set_resources	= noop_set_resources,
@@ -20,6 +23,12 @@ static struct device_operations pci_domain_ops = {
 
 static void set_mmio_dev_ops(struct device *dev)
 {
+	switch (dev->path.mmio.addr) {
+	case APU_UART0_BASE:
+	case APU_UART1_BASE:
+		dev->ops = &cezanne_uart_mmio_ops;
+		break;
+	}
 }
 
 static void enable_dev(struct device *dev)
-- 
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