From af382a77d719ac7e2407c8f47376706a00d32c80 Mon Sep 17 00:00:00 2001
From: Raul E Rangel <rrangel@chromium.org>
Date: Thu, 3 Feb 2022 15:44:48 -0700
Subject: soc/amd/sabrina/psp_verstage: Implement get_uart_base

The Sabrina PSP doesn't support mapping the UART, so add a dummy
function to return NULL.

BUG=b:215599230
TEST=None

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idad8e4874e78bb96730feecb5a7b17334d12217c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/soc/amd/sabrina/psp_verstage/Makefile.inc |  1 +
 src/soc/amd/sabrina/psp_verstage/uart.c       | 11 +++++++++++
 2 files changed, 12 insertions(+)
 create mode 100644 src/soc/amd/sabrina/psp_verstage/uart.c

(limited to 'src/soc/amd')

diff --git a/src/soc/amd/sabrina/psp_verstage/Makefile.inc b/src/soc/amd/sabrina/psp_verstage/Makefile.inc
index 27539dafbc..2338bf5e47 100644
--- a/src/soc/amd/sabrina/psp_verstage/Makefile.inc
+++ b/src/soc/amd/sabrina/psp_verstage/Makefile.inc
@@ -11,6 +11,7 @@ subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage
 
 verstage-y += svc.c
 verstage-y += chipset.c
+verstage-y += uart.c
 
 verstage-y += $(top)/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_startup.S
 verstage-y += $(top)/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_end.S
diff --git a/src/soc/amd/sabrina/psp_verstage/uart.c b/src/soc/amd/sabrina/psp_verstage/uart.c
new file mode 100644
index 0000000000..1c89f10c99
--- /dev/null
+++ b/src/soc/amd/sabrina/psp_verstage/uart.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bl_uapp/bl_syscall_public.h>
+#include <amdblocks/uart.h>
+#include <types.h>
+
+uintptr_t get_uart_base(unsigned int idx)
+{
+	/* Mapping the UART is not supported. */
+	return 0;
+}
-- 
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