From a5cdf75f690c2fb48d00df6ab4e7ba2bfd8a4480 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Wed, 10 Mar 2021 15:47:00 +0100
Subject: soc/amd: move warm reset flag function prototypes to common code

Even though the implementation is different on Stoneyridge compared to
Picasso and Cezanne, the function prototypes are identical, so move them
to the AMD SoC common reset header file.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
 src/soc/amd/cezanne/cpu.c                          | 2 +-
 src/soc/amd/cezanne/include/soc/reset.h            | 9 ---------
 src/soc/amd/cezanne/reset.c                        | 1 -
 src/soc/amd/common/block/include/amdblocks/reset.h | 2 ++
 src/soc/amd/picasso/cpu.c                          | 2 +-
 src/soc/amd/picasso/include/soc/reset.h            | 9 ---------
 src/soc/amd/picasso/mca.c                          | 2 +-
 src/soc/amd/picasso/reset.c                        | 1 -
 src/soc/amd/stoneyridge/cpu.c                      | 1 +
 src/soc/amd/stoneyridge/include/soc/northbridge.h  | 2 --
 src/soc/amd/stoneyridge/mca.c                      | 2 +-
 11 files changed, 7 insertions(+), 26 deletions(-)
 delete mode 100644 src/soc/amd/cezanne/include/soc/reset.h
 delete mode 100644 src/soc/amd/picasso/include/soc/reset.h

(limited to 'src/soc/amd')

diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c
index 6754bba5b9..148dcd8b31 100644
--- a/src/soc/amd/cezanne/cpu.c
+++ b/src/soc/amd/cezanne/cpu.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/cpu.h>
+#include <amdblocks/reset.h>
 #include <amdblocks/smm.h>
 #include <console/console.h>
 #include <cpu/amd/microcode.h>
@@ -12,7 +13,6 @@
 #include <device/device.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>
-#include <soc/reset.h>
 
 /* MP and SMM loading initialization */
 
diff --git a/src/soc/amd/cezanne/include/soc/reset.h b/src/soc/amd/cezanne/include/soc/reset.h
deleted file mode 100644
index 4cb94ced02..0000000000
--- a/src/soc/amd/cezanne/include/soc/reset.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_CEZANNE_RESET_H
-#define AMD_CEZANNE_RESET_H
-
-void set_warm_reset_flag(void);
-int is_warm_reset(void);
-
-#endif /* AMD_CEZANNE_RESET_H */
diff --git a/src/soc/amd/cezanne/reset.c b/src/soc/amd/cezanne/reset.c
index 89b5b809d6..aae76bf4c6 100644
--- a/src/soc/amd/cezanne/reset.c
+++ b/src/soc/amd/cezanne/reset.c
@@ -3,7 +3,6 @@
 #include <arch/io.h>
 #include <cf9_reset.h>
 #include <reset.h>
-#include <soc/reset.h>
 #include <soc/southbridge.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/reset.h>
diff --git a/src/soc/amd/common/block/include/amdblocks/reset.h b/src/soc/amd/common/block/include/amdblocks/reset.h
index b825f471a5..353720c1e0 100644
--- a/src/soc/amd/common/block/include/amdblocks/reset.h
+++ b/src/soc/amd/common/block/include/amdblocks/reset.h
@@ -9,6 +9,8 @@
 
 void do_warm_reset(void);
 void do_cold_reset(void);
+void set_warm_reset_flag(void);
+int is_warm_reset(void);
 
 static inline __noreturn void warm_reset(void)
 {
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index 088660ea7a..36bbf0aa60 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/cpu.h>
+#include <amdblocks/reset.h>
 #include <amdblocks/smm.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/mp.h>
@@ -12,7 +13,6 @@
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
 #include <soc/cpu.h>
-#include <soc/reset.h>
 #include <soc/smi.h>
 #include <soc/iomap.h>
 #include <console/console.h>
diff --git a/src/soc/amd/picasso/include/soc/reset.h b/src/soc/amd/picasso/include/soc/reset.h
deleted file mode 100644
index fb47068ea0..0000000000
--- a/src/soc/amd/picasso/include/soc/reset.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_PICASSO_RESET_H
-#define AMD_PICASSO_RESET_H
-
-void set_warm_reset_flag(void);
-int is_warm_reset(void);
-
-#endif /* AMD_PICASSO_RESET_H */
diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c
index e16d0a19e3..c21f4f1072 100644
--- a/src/soc/amd/picasso/mca.c
+++ b/src/soc/amd/picasso/mca.c
@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/reset.h>
 #include <cpu/x86/msr.h>
 #include <acpi/acpi.h>
 #include <soc/cpu.h>
-#include <soc/reset.h>
 #include <console/console.h>
 #include <arch/bert_storage.h>
 #include <cper.h>
diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c
index 89b5b809d6..aae76bf4c6 100644
--- a/src/soc/amd/picasso/reset.c
+++ b/src/soc/amd/picasso/reset.c
@@ -3,7 +3,6 @@
 #include <arch/io.h>
 #include <cf9_reset.h>
 #include <reset.h>
-#include <soc/reset.h>
 #include <soc/southbridge.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/reset.h>
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index d943deb69a..e00763753a 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/reset.h>
 #include <amdblocks/smm.h>
 #include <cpu/amd/msr.h>
 #include <cpu/cpu.h>
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index d00f5660d7..8eb3a25825 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -86,7 +86,5 @@
 void domain_enable_resources(struct device *dev);
 void domain_read_resources(struct device *dev);
 void fam15_finalize(void *chip_info);
-void set_warm_reset_flag(void);
-int is_warm_reset(void);
 
 #endif /* AMD_STONEYRIDGE_NORTHBRIDGE_H */
diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c
index 0f2900cb94..b1f955fcc3 100644
--- a/src/soc/amd/stoneyridge/mca.c
+++ b/src/soc/amd/stoneyridge/mca.c
@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/reset.h>
 #include <cpu/x86/msr.h>
 #include <acpi/acpi.h>
 #include <soc/cpu.h>
-#include <soc/northbridge.h>
 #include <console/console.h>
 #include <arch/bert_storage.h>
 #include <cper.h>
-- 
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