From 956432cbb7f0a5a1618fb1111158cf3a8ede5f60 Mon Sep 17 00:00:00 2001 From: Robert Zieba Date: Tue, 25 Oct 2022 10:30:14 -0600 Subject: soc/amd/cezanne: Update GPP clk req code to use ARRAY_SIZE Currently the GPP clk req configuration code assumes that the size of the config array is `GPP_CLK_OUTPUT_COUNT`. This commit changes that code to use the `ARRAY_SIZE` macro instead. BRANCH=guybrush BUG=b:250009974 TEST=Ran on nipperkin device, verified that clk req settings are correct. Change-Id: I3ff555843c6f5aa38acd8300e0dc2da4e33fb4b7 Signed-off-by: Robert Zieba Reviewed-on: https://review.coreboot.org/c/coreboot/+/68866 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Felix Held --- src/soc/amd/cezanne/fch.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/amd') diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 7227d20be8..1ceb8bc7b9 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -153,7 +153,8 @@ static void gpp_clk_setup(void) uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); - pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], GPP_CLK_OUTPUT_COUNT); + pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], + ARRAY_SIZE(cfg->gpp_clk_config)); for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); -- cgit v1.2.3