From 8b894242e727539ed40436d20bd87a097d371845 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 26 May 2022 15:42:59 +0300 Subject: soc,sb/amd: Change SPI controller resource MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This replaces IORESOURCE_SUBTRACTIVE with IORESOURCE_RESERVE. Change-Id: Ib3d934ca704273daacbeb3c52412bf04e2be7217 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/64695 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/lpc/lpc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/soc/amd') diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 0eda7f2fd8..68e1fce960 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -117,8 +117,7 @@ static void lpc_read_resources(struct device *dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* Add a memory resource for the SPI BAR. */ - fixed_mem_resource_kb(dev, 2, SPI_BASE_ADDRESS / KiB, 1, - IORESOURCE_SUBTRACTIVE); + mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB); res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; -- cgit v1.2.3