From 6998ee069a33ab56307c43a4108276a020fc713f Mon Sep 17 00:00:00 2001 From: Robert Zieba Date: Mon, 19 Sep 2022 10:26:51 -0600 Subject: soc/amd/cezanne: Set up SoC-specific XHCI definitions Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI. BRANCH=guybrush BUG=b:186792595 TEST=builds Signed-off-by: Robert Zieba Change-Id: I15e9c06cd38ac858b861a4d19626664704af7541 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67939 Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/Kconfig | 1 + src/soc/amd/cezanne/include/soc/xhci.h | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 src/soc/amd/cezanne/include/soc/xhci.h (limited to 'src/soc/amd') diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 170bc49e39..046fd233f4 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -70,6 +70,7 @@ config SOC_AMD_CEZANNE select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_PCI select SOC_AMD_COMMON_FSP_PRELOAD_FSPS + select SOC_AMD_COMMON_BLOCK_XHCI select SSE2 select UDK_2017_BINDING select USE_DDR4 diff --git a/src/soc/amd/cezanne/include/soc/xhci.h b/src/soc/amd/cezanne/include/soc/xhci.h new file mode 100644 index 0000000000..c590195731 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/xhci.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_XHCI_H +#define AMD_CEZANNE_XHCI_H + +#include + +#define SOC_XHCI_0 DEV_PTR(xhci_0) +#define SOC_XHCI_1 DEV_PTR(xhci_1) +#define SOC_XHCI_2 NULL +#define SOC_XHCI_3 NULL +#define SOC_XHCI_4 NULL +#define SOC_XHCI_5 NULL +#define SOC_XHCI_6 NULL +#define SOC_XHCI_7 NULL + +#endif /* AMD_CEZANNE_XHCI_H */ -- cgit v1.2.3