From 696f4ea0f52b37a299197edfc71acb422151834a Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 8 Jan 2021 11:48:52 -0800 Subject: soc/amd/cezzane: Add a minimal chipset tree This change adds a minimal chipset tree with only two devices: 1. Domain 2. GNB root complex This allows sconfig to generate the config structure for SoC root device that is used by config_of_soc(). Change-Id: I7e08ecf4b9556dc9325bd5a6a51566a949ceb73f Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/49245 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons Reviewed-by: Jason Glenesk --- src/soc/amd/cezanne/Kconfig | 4 ++++ src/soc/amd/cezanne/chipset.cb | 5 +++++ 2 files changed, 9 insertions(+) create mode 100644 src/soc/amd/cezanne/chipset.cb (limited to 'src/soc/amd') diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 22d0c3ac61..afee1efd70 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -26,6 +26,10 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H +config CHIPSET_DEVICETREE + string + default "soc/amd/cezanne/chipset.cb" + config EARLY_RESERVED_DRAM_BASE hex default 0x2000000 diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb new file mode 100644 index 0000000000..49bd0c8b18 --- /dev/null +++ b/src/soc/amd/cezanne/chipset.cb @@ -0,0 +1,5 @@ +chip soc/amd/cezanne + device domain 0 on + device pci 00.0 alias gnb on end + end +end -- cgit v1.2.3