From 57419de1879ca5d40669fb2690428bc0e0addb31 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 14 Jan 2021 01:16:56 +0100 Subject: soc/amd/cezanne: add basic romstage This currently only initializes the console, calls into the FSP driver that then calls into FSP-M and then jumps to ramstage after the FSP-M returns. Right now, this mainly unblocks the FSP-M development. Change-Id: I9f3cdaac573e365bb4d59364d44727677f53e91b Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/49446 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/romstage.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src/soc/amd') diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index 52ff0f8e41..509addfa52 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include +#include void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { @@ -9,4 +11,15 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) asmlinkage void car_stage_entry(void) { + post_code(0x40); + console_init(); + + post_code(0x41); + + u32 val = cpuid_eax(1); + printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + + fsp_memory_init(false); /* no S3 resume yet */ + + run_ramstage(); } -- cgit v1.2.3