From 230dbd6d3c194d9f839d31a0a579ef99befdd097 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 28 Jan 2021 23:40:52 +0100 Subject: soc/amd/cezanne: add empty ramstage FCH support Signed-off-by: Felix Held Change-Id: I38c6961b65b89cb57ff80e491bf8973be4e12eeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/50094 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/Makefile.inc | 1 + src/soc/amd/cezanne/chip.c | 4 ++++ src/soc/amd/cezanne/fch.c | 11 +++++++++++ src/soc/amd/cezanne/include/soc/southbridge.h | 7 +++++-- 4 files changed, 21 insertions(+), 2 deletions(-) create mode 100644 src/soc/amd/cezanne/fch.c (limited to 'src/soc/amd') diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index bcf1d722c4..9422a4db31 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -25,6 +25,7 @@ romstage-y += romstage.c romstage-y += uart.c ramstage-y += chip.c +ramstage-y += fch.c ramstage-y += fsp_params.c ramstage-y += gpio.c ramstage-y += reset.c diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index 70df778aff..fd930896a7 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -2,6 +2,7 @@ #include #include +#include #include #include "chip.h" @@ -12,10 +13,13 @@ static void enable_dev(struct device *dev) static void soc_init(void *chip_info) { fsp_silicon_init(false); /* no S3 support yet */ + + fch_init(chip_info); } static void soc_final(void *chip_info) { + fch_final(chip_info); } struct chip_operations soc_amd_cezanne_ops = { diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c new file mode 100644 index 0000000000..f853ecee93 --- /dev/null +++ b/src/soc/amd/cezanne/fch.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void fch_init(void *chip_info) +{ +} + +void fch_final(void *chip_info) +{ +} diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 2a294e96ef..6949fa57b3 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -30,9 +30,12 @@ /* IO 0xf0 NCP Error */ #define NCP_WARM_BOOT (1 << 7) /* Write-once */ -void enable_aoac_devices(void); -void wait_for_aoac_enabled(unsigned int dev); void fch_pre_init(void); void fch_early_init(void); +void fch_init(void *chip_info); +void fch_final(void *chip_info); + +void enable_aoac_devices(void); +void wait_for_aoac_enabled(unsigned int dev); #endif /* AMD_CEZANNE_SOUTHBRIDGE_H */ -- cgit v1.2.3