From 12deac1421b4832b8a63da8dea5da7f5d11ea263 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Tue, 1 May 2018 14:44:14 -0600 Subject: soc/amd/stoneyridge: remove sb_set_readspeed function The sb_set_readspeed() was touching the wrong register and the read speed settings are handled by sb_set_spi100(). Nothing was using the function, so remove it. Change-Id: I23b20cf559ee759ba94d49ff6810a9baa64e86fb Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/25969 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson Reviewed-by: Martin Roth --- src/soc/amd/stoneyridge/include/soc/southbridge.h | 1 - src/soc/amd/stoneyridge/southbridge.c | 9 --------- 2 files changed, 10 deletions(-) (limited to 'src/soc/amd') diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 96826e330c..0a23fcacd4 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -379,7 +379,6 @@ void sb_acpi_mmio_decode(void); void sb_pci_port80(void); void sb_read_mode(u32 mode); void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); -void sb_set_readspeed(u16 norm, u16 fast); void sb_tpm_decode(void); void sb_tpm_decode_spi(void); void lpc_wideio_512_window(uint16_t base); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index a767e0c297..eb8820f250 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -442,15 +442,6 @@ void sb_disable_4dw_burst(void) & ~SPI_RD4DW_EN_HOST); } -void sb_set_readspeed(u16 norm, u16 fast) -{ - uintptr_t base = sb_spibase(); - write16((void *)base + SPI_CNTRL1, (read16((void *)base + SPI_CNTRL1) - & ~SPI_CNTRL1_SPEED_MASK) - | (norm << SPI_NORM_SPEED_SH) - | (fast << SPI_FAST_SPEED_SH)); -} - void sb_read_mode(u32 mode) { uintptr_t base = sb_spibase(); -- cgit v1.2.3